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MAY 31st, 2005
Ansoft Corporation Fourth Quarter Revenues Increase 22%
Ansoft Corporation (NASDAQ:ANST), a broad based EDA company with design tools for the development
of integrated circuits, automotive systems, cellular phones, printed circuit boards and power electronics reported that its
revenue rose 22 percent in its fourth quarter of fiscal 2005, which ended April 30, 2005. The company reported revenues of
$21.7 million compared to $17.8 million in the fourth quarter of 2004. For the entire year, the company reported revenues
of $67.7 million, compared to $54.7 million reported in its last fiscal year.
Nicholas Csendes, Ansoft's President and CEO sees continued growth
and profitability in Ansoft's next fiscal year, "For the next fiscal year, we anticipate revenue growth of around 15% as well
as increasing profitability of around 25%."
MAY 27th, 2005
Golden Gate Technology Inc., an EDA company focused on integrated
circuit design algorithms that reduce power consumption, has added Power Optimize Gold and Power Plan Gold to its designer's
tool kit. Through the generation of complex power grids, multi-voltage islands and the company's WiresFirst technology, the
company indicates that significant savings in power can be achieved. In support of the design tools' power capabilities, Kelvin
Chun, Director of Design Center Application Engineering at Oki Semiconductor pointed to their internal benchmarks, "We have
over 50 successful tapeouts with Power Plan Gold. From our benchmarks, we determined that, out of all the tools we evaluated,
Power Optimize Gold consistently produced exceptional results."
Two basic components of power consumption are central to the operation
of the company's WiresFirst patented power optimization methodology. These are wire related power consumption and transistor
related power consumption. According to the company, wire power consumption becomes more critical as process feature size
scale. Specifically the company estimated that "wires account for 5x more power consumption than transistors at the 90 nanometer
node, and 30x more power consumption than transistors at 35 nanometers."
Both Power Plan Gold and Power Optimize Gold are available now and
are priced at $115,000 and $395,000 respectively for time-based licenses.
MAY 26th, 2005
Infineon Technologies, one of the largest semiconductor companies
in Europe, with funding from Apax Partners, has spun-out its internal EDA division. The division, the Circuit Verification
Environment division, will become One-Spin Solutions GmbH.
The new company, which develops early stage verification solutions
for the design of integrated circuits, will consist of 25 employees. The new company is expected to increase its staff with
the 14 million Euros it has received from Apax Partners.
OneSpin already has a customer base. Customers include Infineon,
which plans to remain a customer and license OneSpin’s product. Other customers listed include Siemens, Bosch, Lucent
Germany and Rolls Royce.
Wolfram Buttner, CTO at OneSpin Solutions, indicated that one of
the goals of the company, besides that implied by its names, was to create error free designs, "Today, designs free
of functional errors are becoming a realistic goal for chip manufacturers. In fact, we're proving that it's both technically
as well as commercially possible to develop a modern microcontroller without functional errors."
MAY 24th, 2005
Cellular IC Design Tool Developed to Address Cell Phone
Chip Market
One way to address power consumption in cellular phones is to build an EDA design tool
specifically for that task - veering from the traditional EDA product development strategy of one size fits all. Azuro, which looks
to be on that course, is addressing the power problem in cell phones, a market estimated at about 600 million units
a year, with its first product, PowerCentric.
The company believes that the way to win in the market is to offer
the lowest power solution, which translates to the longest continuous talk time. Paul Cunningham, CEO at Azuro explained,
"The wireless device market is evolving extremely fast, driven by short product lifecycles and rapidly increasing functionality.
The consumer's insatiable appetite for more talk time, more play time, and increased functionality, in ever smaller packages,
has elevated power to the key issue for many digital chip design teams. Azuro is committed to helping these design teams significantly
reduce the power consumption of their chips."
Paul went on to talk about the specific features of the design tool,
"PowerCentric delivers a truly unified clock gating and clock tree balancing engine that seamlessly replaces clock tree synthesis
in existing industry design flows." Steev Wilcox, Chief Architect at Azuro noted the benefits of the vectorless active reporting
engine in the design tool, "Our SASim vectorless power estimation technology enables PowerCentric to implement the best trade-offs
and save the most power during optimization. You cannot optimize what you cannot accurately measure. "
Azuro has already won over Broadcom, one of the largest fabless
semiconductors in the world. Steve Barlow, Senior Director of Engineering at Broadcom's Mobile Multimedia Products group,
confirmed Mr Cunningham's assessment, "Power dissipation has become increasingly important to the semiconductor industry as
consumers demand ever more talk time, play time, and functionality in their next-generation mobile phones and portable devices.
Meeting power requirements is one of the biggest challenges facing chip design teams today."
MAY 23rd, 2005
VaST Closes $12 Million - Plans R&D
and Field Support
VaST Systems Technology Corporation (VaST), an EDA tools company, which provides system design
tools to semiconductor, automotive electronics, and consumer electronics companies, has closed its Series C funding round,
valued at $12 million. Foundation Capital led the round, joined by Mohr Davidow Ventures and Allen & Buckeridge.
Mike Schuh, General Partner at Foundation Capital, who now is also
a member of VaST's board, noted that VaST's design tools reduced the design development time of SoCs about 25 percent., “Foundation
was very pleased to be able to lead this C round for VaST,” remarked Mike Schuh, Foundation Capital general partner.
“Embedded system design automation is critical and is today a dramatically underserved area. With system on a chip (SoC)
functionality rapidly migrating from hardware to embedded software, VaST’s virtual system prototypes in software, which
run nearly as fast as the hardware device and are cycle accurate, are providing a huge competitive advantage for their customers.
With VaST, users are starting software development coincident with the hardware development and cutting nine to twelve months
off their development cycles.”
MAY 23rd, 2005
Stone Pillar Reduces Test Plan Time 90 Percent
With its EDA market plan, Stone Pillar Technologies, Inc. has opened up the doors to the test
plan market. The company has just reported that National Semiconductor (NASDAQ: NSM) , one of the world's leading analog
and mixed signal semiconductor companies, has adopted its TestPlanManager for the automation of test flows.
According to Mark Poulter, electrical test manager at National Semiconductor's
Advanced Process Technology Development Group, National reduced the engineering time for the test flow creation time
from a week to just a half day. Besides the 90 percent in test development time saved, he noted a number of other benefits
that test engineers can appreciate, "TestPlanManager speeds the development of test flows and reduces errors by
automating many of the steps that previously had to be painstakingly implemented by hand. Skilled test engineers can
now focus on real technological challenges rather than on the administrative tasks of manual data entry that do not add value
for technology development."
Besides the automation of the test flow creation process, TestPlanManager
also earns credits with its ability to target the test plan for any one of a number of automated test equipment (ATE) platforms.
MAY 20th, 2005
Synopsys, Inc. (NASDAQ: SNPS), has released results for its second
quarter, which ended April 30 2005. The company's revenue for the quarter increased 1 percent on a quarterly sequential basis,
but declined 17 percent on a quarterly year-over-year basis. For the second quarter of fiscal 2005, revenues were $244.3 million
compared to $294.6 million for the second quarter of fiscal 2004. For its latest six months, Synopsys reports that revenue
was $485.6 million compared to $579.9 million for the same period in fiscal 2004. Synopsys stated that "year-over-year comparisons
reflect the company's shift to an almost-fully ratable license model initiated in the fourth quarter of fiscal 2004, under
which most of the company's license revenue is recognized over time rather than upfront in the quarter shipped. As a result,
in the most recent quarter more than 90% of revenue came from backlog." A review of Synopsys numbers indicate that Synopsys
up-front license revenue declined substantially, year-over-year.
Synopsys also reported for its 2005 fiscal year a target revenue
in the range of $960 million to $990 million. These estimates include the effect of the acquisition of Nassda Corporation,
another EDA company.
MAY 20th, 2005
Fluent, Inc, a computational fluid dynamics design tool company,
has released version 4.1 of its Icepro analysis tool. The tool permits the conversion of arbitrary CAD models into thermal
models. The new version contains a conversion model that is used to make a CAD model thermal analysis friendly - eliminating
many of the tedious manual steps that are involved in that process. The tool is also now capable of importing flow objects
such as holes, vents and fans, and even arrays of holes, also known as vents or grilles.
Icepro 4.1, which is available now, is priced at $3000.00 per user
node.
MAY 19th, 2005
Silicon Design Systems Introduces K-Route
Silicon Design Systems (SDS), a newcomer to the EDA market, has come out with K-Route, targeted
at one of the larger segments of the EDA tool market, interconnect chip routing.
K-Route's Interconnect Synthesis tool offers a different approach
to the layout problem. The company states that its router is placement independent . The tool in order to optimize the routing
layout makes use of an incremental placement engine, which allows for the optimization of speed and power consumption, without
sacrificing design time and silicon area.
Jacob Greidinger, Vice President of R&D at Silicon Design Systems
talked about the history of the products development, "Silicon Design Systems, as a design service firm, developed analysis
and optimization tools for more than 10 years to serve our own internal needs. Two years ago, we decided to apply our expertise
externally and began coding and integration of this brand new approach to interconnect synthesis. K-Route, the result of this
24 month concentrated effort, conquers traditional routing inefficiencies with dynamic new methodology that automates the
entire process to achieve highest-quality results. We view it as a 'killer application' that takes the guesswork out of physical
closure."
So far, K-Route is under consideration at two fabless chip companies,
Zoran Microelectronics and Transchip. Nir Sever, Sr. Director, VLSI Design and Technology at Zoran Microelectronics, commented
on his experience with SDS' technology, "Our company develops devices for consumer electronics applications with an aggressive
die size target. The idea of concurrently optimizing our designs during the routing process, rather than afterwards, appeals
to us as it can potentially allow us to achieve higher utilizations. K-Route holds great promise for us, and we are actively
investigating its benefits. We have used SDS technology in the past to achieve substantial value in terms of die size and
predictability."
Eli Assoolin, CAD and Backend Manager at TransChip, a CMOS image
company, indicated that the prospect of better timing and power consumption in the context of the special routing needs of
CMOS image sensor chips was a major talking point, "One of the biggest challenges in our CMOS image sensor chip design is
the floor-plan, which must take into account the embedded sensor array optics and the ISP. Due to the size and centrality
of our imager array, we cannot afford to compromise on router quality which must accommodate the special shape of the digital
logic. Therefore, we are evaluating the most promising state-of-the-art technologies such as Silicon Design Systems' K-Route,
which shows potential in providing better results in terms of area timing and power consumption."
K-Route, which can be interfaced to existing integrated circuit
physical design flows, is available now and priced at $495 K for a one-year license.
MAY 19th, 2005
Sarnoff Offers Snap-On ESD
IO Protection for Chip and IP Designs
Sarnoff Europe, which developed a silicon area optimized electrostatic discharge (ESD) design
several years ago, has now released ESDdoctor. The new tool, which includes the license for the actual design and layout of
the circuit, was developed to simplify the ESD protection process for designs in progress.
Koen Verhaege, Senior Director of Sarnoff's Integrated Circuit Systems
& Services Business Unit, gave an overview of the benefits of the product and remarked on just how easy it is to use,
"ESDdoctor is just what the name implies - a fast and trustworthy cure for ESD challenges or problems that would otherwise
slow up the completion of a design, causing critical market introduction delays and expensive rework and remasking. It's almost
as easy as a cut-and-paste operation in a word processing program. Just drop in the core and the ESD design is complete. "
As a note of reassurance to those that deal in the complex world of chip technology, he added, "The big advantage of Sarnoff's
ESDdoctor solutions is: you drop them in and they work."
ESDdoctor is based on Sarnoff's mature ESD technology, known worldwide
as TakeCharge. TakeCharge has been time tested in a number of different CMOS processes and the now popular SOI process. Sarnoff
Europe lists its licensees, which include several tier one semiconductor companies, as Toshiba, Sony, Epson, OKI, JRC, Hynix,
Infineon, Altera, PMC-Sierra, Renesas, Ricoh, Matsushita, and Scintera.
MAY 18th, 2005
Sigrity Announces Solution to Chip Package Cosimulation Problem
Sigrity, Inc., an EDA company involved in the chip, IC package and printed circuit markets,
announced CoDesign Studio, a design tool specifically targeted to solve design problems that are a result of the interrelationship
of chip package and the silicon die. The new tool is used to analyze power integrity of the silicon die and the chip package
that the designer intends to finally place the die into to. The tool combines the power of Sigrity's SPEED 2000 used for electrical
analysis of packages and the XcitePI tool used for power grid analysis of the actual silicon chip.
Jiayuan Fang, President of Sigrity underlined the need for such
tools as the operating speeds of chips continue to increase, "Power integrity issues continue to be a critical concern for
high-speed designs. Most current EDA tools inadequately represent chip/package interactions, often leading to incorrect or
misleading power analysis results. Sigrity helps companies overcome these deficiencies by co-simulating the complete chip
and entire package to ensure correct operation and reduce design iterations."
CoDesign Studio will be available in June 2005 and priced for existing
customers at $30,000.00.
MAY 17th, 2005
Samsung's Virtually Exploitive EDA Tool to Save $30 Million
in Chip Costs
Samsung Electronics Co., Ltd., well know for its semiconductors
and cell phones, has developed a new virtual prototype tool, which will give designers the ability to avoid back-end design
problems before the actual design implementation process begins. The tool, called ESCORT/SRSIM, which stands for Estimation
of Chip Performance on Process Tolerance/Samsung Reliability Simulator, is an advanced feasibility analysis tool that allows
for high end simulation analysis early in the design cycle.
Samsung notes that the ESCORT software results in increased wafer
yields. Furthermore, the SRSIM tool can determine if transistors will fail in the field. Part of the reason for increased
yields and reliability is that the tools permits transistor level simulations at the preliminary design stage - as opposed
to the final stages of the design. Samsung estimates that the new tools will save about $30 million a year in its operational
costs. Savings estimates are based on reduced design time and increased wafer yields. Samsung says chip development time is
reduced by at least four weeks, mainly because delays from redesign and mask corrections are eliminated.
The simulator can be used on memory chips, display drivers, image
sensors and large scale system on chip (SOC).
MAY 16th, 2005
Pyxis, EDA Layout Start Up, Opens Office In Santa Clara Valley
Pyxis Technology, founded in 2004, plans to open an office in the heart of the Santa Clara
Valley, known by technologists as the Silicon Valley. Pyxis is in the midst of developing physical design software for the
layout and routing of integrated circuits. The company received Series A funding from Austin Ventures and CMEA Ventures.
Newly appointed CEO and President of the company, Naeem Zafar, entered
his position with a profound statement about the company's product development plans, "Pyxis' technology is compelling, and
its founding team is a unique blend of ace chip designers and EDA developers that have worked together in physical chip design
for many years. Their frustration at seeing a fundamental lack of architecture that can address and scale with the new challenges
of nanometer IC design enticed them to start Pyxis, and the results are very encouraging."
A recurring problem in the chip design world is the inability of
old EDA tools to successfully address design issues associated with newly introduced process technologies. This has resulted
in many chip design failures. Chip companies must design new chips based on new chip manufacturing process technologies about
every two years.
MAY 13th, 2005
Spansion Selects Prolific's Automated Cell Design
Tool - Sites Power and Flexibility
Spansion LLC, one of the worlds top flash chip manufacturers, and a joint venture of AMD and
Fujitsu, two tier one semiconductor companies, has selected Prolific Incorporated's ProGenesis automated cell design software.
Spansion plans to use the design tool to automate and expedite the design of standard cells used in its flash integrated circuits.
Jim Thomas, Spansion's Vice President of Product Development, explained
the transition of Prolific from a service provider to an EDA tool provider, "As Spansion expands its product portfolio, we
are finding significant advantages to having control over our library IP. What began as a library service deal became a software
purchase when we saw ProGenesis' power and flexibility." Joaquin Bartra, CAD application manager at Spansion, elaborated further,
"ProGenesis gives us the ability to rapidly prototype, create, and customize cell libraries that are perfectly suited to the
final products in which they'll be used. The tool's flexibility allows us to explore multiple options and make the right design
choices."
MAY 12th, 2005
Aprio Announces DFM Partnership with NEC
Aprio Technologies Inc.,
a Design For Manufacturing (DFM) EDA tools company, has entered into an agreement with NEC Electronics. Aprio's will collaborate
on and incorporate reticle enhancement technology (RET) into NEC Electronics semiconductor manufacturing flow. Kazu Yamada,
Associate Vice President and General Manager of NEC's Technology Foundation Development Division commented on Aprio's technology,
"We are quite impressed with the technology Aprio has developed so far. We feel they truly understand DFM issues and are eager
to work with them on extending and deploying their solutions to give NEC Electronics a competitive edge in advanced semiconductor
processes."
Aprio Technologies, based
in Santa Clara California, was founded in 2003.
MAY 11th, 2005
Xpedion Sees RF EDA Accounts Rising in China
Xpedion Design Systems, Inc. has reported that it has secured Rising
Microelectronics, a fabless chip company based in China, as a customer for its GoldenGate RFIC simulator, a chip design tool
used for transistor level analysis of radio frequency (RF) based integrated circuit (IC) designs.
Rising Microelectronics, has already begun using the frequency domain
simulation features of GoldenGate to analyze its RF transceiver designs. According to Jianci Chen, VP of Marketing at Rising
Microelectronics."GoldenGate has proven to be a valuable asset to our RFIC development. Our team was able to quickly install
and start using GoldenGate to produce accurate results on large RF blocks and complete RF chains. Xpedion has also provided
excellent technical support to our various design locations."
Paul Pickering, Xpedion's VP of Sales, indicated that the account
win, established Xpedion as a global EDA company, "Our engagement with Rising Microelectronics represents a significant milestone
for Xpedion. The product endorsement of GoldenGate by the Rising team completes our goal to have active customers in every
major IC design geography."
Rising Micro Electronics Co., Ltd. was founded in 2003 and funded
by the Guangdong Rising Asset Management Co., Ltd. Rising has its headquarters in China, at Guangzhou Tianhe Hi-Tech Park,
as well as design facility in the United States. Rising is presently focused on wireless and wired communication chip design
and supporting IP Core development.
MAY 10th, 2005
Synopsys Brings Supply Drop Analysis to Front-End Design
Synopsys, Inc. (NASDAQ: SNPS ) has introduced PrimeRail, to its line of power analysis and sign-off tools.
PrimeRail, according to the company, permits a design engineer to evaluate power supply voltage drop and electromigration
effects at the front-end, during floorplanning, and at the back-end, for transistor-level GDSII-based power network sign-off.
The tool also permits the designer also to determine the effect of on-chip decoupling capacitors as well as package parasitics
on internal voltage drop. The design software is based on a hybrid technology, which simulates RLC networks, but at the same
time minimizes simulation memory.
Virage Logic's CTO, Alex Shubat, commented on the need for an accurate power network
sign-off tool in an embedded memory SoC design environment, "Today, embedded memory IP contributes up to 70 percent of a chip's
area -- and accurate power network sign-off is essential to verify these memories for high reliability and yield. We will
continue collaborating with Synopsys on our memory verification flow, and will look to standardize on PrimeRail for sign-off
of our 90 and 65-nanometer Area, Speed and Power (ASAP) Memory and Self-Test and Repair (STAR) Memory System product lines.
PrimeRail will help ensure our mutual customers are able to rapidly complete their designs based on Virage Logic's standalone
memory products or its IPrima Foundation semiconductor IP platform offering."
PrimeRail is tightly integrated with
Synopsys' Galaxy Design Platform, a comprehensive tool set for the design of integrated circuit chips.
MAY 9th, 2005
FishTail Design Automation, an EDA company focused on timing constraint
issues, has received a patent related to the generation of timing exceptions from integrated circuit designs. The patent has
the title "Automated approach to constraint generation in IC design." Ajay Daga, CEO at FishTail Design Automation, related
the patent to what the company's customers have said about the uniqueness of FishTail's Focus design tool, "The patent that
has been awarded to us confirms what our customers acknowledged when we launched the Focus product early last year -- that
we have achieved a fundamental technical breakthrough in the EDA industry. We are the only game in town when it comes to a
production-ready tool for the generation of timing exceptions on multi-million gate designs. Our products are being used worldwide
with great success by major semiconductor and networking companies."
MAY 6th, 2005
Laflin Enters EDA Market with GDS and Photomask DFM Tools
Laflin Limited, an EDA company founded just two months ago, March
8, 2005, announced its HOTSCOPE GDS and photomask data viewer. HOTSCOPE, developed by Dai Nippon Printing (DNP) of Japan,
one of the world's largest printing companies, is supported exclusively in the United States by Laflin. Naoya Hayashi, General
Manager, Electronic Device Laboratory at DNP described the problem current data viewers face in the latest chip design environment,
"Growing chip complexity, combined with data preparation steps such as optical proximity correction (OPC) and dummy pattern
insertion required for deep submicron manufacturing processes have driven chip GDS and photomask data sizes into the 10s of
gigabyte range. Conventional EDA data viewers are incapable of handling such large data sets with reasonable response time
and memory usage." Laflin indicates, on the other hand, that HOTSCOPE has file open times that are measured in minutes and
not hours and requires memory in the 100s of MB range. Rick Ader, President of Laflin spoke about acceptance of HOTSCOPE in
the United States, "We're excited to provide our customers best-in-class solutions in the physical design and manufacturing
area. After only a few short weeks of promoting HOTSCOPE, we are already in the midst of three customer evaluations and have
many more potential customers with strong interest in the technology. With HOTSCOPE and our relationship with JEDAT, Laflin
is off to a great start."
HOTSCOPE is already in production use in Japan and Taiwan. JEDAT,
also known as Japan EDA Technologies Inc. is a distributor for HOTSCOPE.
MAY 5th, 2005
CebaTech Inc., a company with Intellectual Property(IP) cores
and EDA tools to facilitate the implementation of communication protocols into integrated circuit designs, has closed a $4.5
million Series B funding round. The company, which is based in New Jersey, was funded through NJTC Venture Fund, SAS Investors
and 2M Technology Ventures.
Robert Chefitz, partner at SAS Investors, praised the founder's
background, Tim Sulivan and his team, "Tim was an Entrepreneur-in-Residence at SAS Investors in 2003. His credibility was
well complemented by a top notch team that had more than a dozen IC design wins in the last decade, and the industry pain-point
related to simulating and testing communication protocols with existing EDA tools is a well recognized one. These factors
led us to close the Series-A investment in less than 75 days when Tim had pitched the Series-A investment opportunity to SAS
Investors a year ago. Since then CebaTech team has surpassed all our expectations."
Robert Chefitz, partner at NJTC Venture Fund, and now a board member
of CebaTech, elaborated on the company's product and space, " In addition to revolutionizing the way communication chips are
designed, the team is targeting to realize paradigm-shifting protocol-based communication products in the IPSec/iSCSI/Packet-Filtering
space."
MAY 5th, 2005
Applied Wave Research, Inc. (AWR), an EDA tools company, which offers
tools for the high frequency end of the electronics market, reported that it has obtained its sixth consecutive year of double-digit
bookings growth, and has returned to profitability. The company also indicated that it had record product revenues in Europe,
North America and Japan and that its latest quarter ended March 31 saw record bookings and revenues. James Spoto, President
and CEO of AWR gave specific numbers and the company's battle to overcome an uncertain economy, "Fiscal year 2005 was the
most successful in AWR's history, with a resounding 38% increase in product bookings over FY2004. Our steady and impressive
growth in an uncertain economy over the past six years bears out our conviction that the EDA market is demanding a completely
new solution to meet the increasingly complex requirements for the design of next-generation communications products. We are
very pleased with our results and look forward to another successful year."
AWR also added new customers. These included Astra Microwave Products,
BOE Hydis, Eagle Test Systems, Inc. and Silicon Laboratories, a major supplier of integrated circuits to the cellular
market. AWR's design tools, which include Microwave Office 2004, Analog Office 2004 and Vision System Simulator 2004
offer features and libraries that address ultra wide band (UWB), wireless local area networks (WLAN) and 3G and 4G cellular
standards.
MAY 4th, 2005
Mentor Graphics Corporation (NASDAQ:MENT) had first quarter revenue
of $164.3 million compared with $164.4 million for the same quarter a year ago. Walden C. Rhines, CEO and chairman of Mentor
Graphics commented on the quarter's results, "Weakness in the business was driven primarily by softness in demand from semiconductor
companies, while demand from system businesses was better. As a result, Mentor systems products like FPGA synthesis, embedded
software and selected PCB products performed well. On the other hand, Calibre product line bookings were particularly weak
in the quarter. We expect strength in this product line in the second half of the year based upon the number of current customer
engagements."
Gregory K. Hinckley, President at Mentor Graphics indicated that
seasonal trends now favored the fourth quarter, "As the drive to time-based licensing continues, our business is increasingly
driven into the fourth quarter. While we are not satisfied with our first quarter performance, our second half continues to
look solid."
For the quarter, system and software revenue declined to $91.6 million
over last years $94.5 million. Service and support revenue increased about $3 million.
MAY 3rd, 2005
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) announced its
revenue increased 10 percent for its latest quarter. Revenues were $293 million compared to $266 million for the first quarter
of 2004. Cadence also reported for its latest quarter that over twenty customers selected its Encounter RTL Compiler product.
For next quarter, the company forecasts revenue in the range of
$300 million to $310 million.
MAY 2nd, 2005
Magma Design Automation Inc. (Nasdaq:LAVA), further advanced its
position in the EDA market with the announcement of its latest quarterly and annual revenues. The company for its fiscal year
ended March 31, 2005, reported revenue of $145.9 million, compared to $113.7 million for the fiscal year ended March 31, 2004.
Sequentially, Magma saw a 5 percent gain. For the fourth quarter ended March 31, 2005, Magma reported revenue of $35.7 million
compared to $34.0 million for the same quarter a year ago.
Rajeev Madhavan, CEO at Magma, highlighted the company's record
bookings, "The year we just completed included many highlights for Magma. Our fiscal 2005 revenue was another annual record
and our bookings in the most recent quarter were also the best in Magma history. With the work our product teams have put
into our Cobra development project, we're looking forward to even greater accomplishments in fiscal 2006."
For Magma's fiscal 2006 first quarter, which ends July 3, 2005,
the company has forecast total revenue somewhere between $35 million to $39 million.
APRIL 29th, 2005
Altium Bases FPGA Design Tools on Verific EDA Component
Software
Altium has chosen Verific Design Automation's hardware description
language (HDL) Component Software for its Nexar design tools used for the building of FPGA based integrated circuits. Altium
indicated that its Nexar product greatly simplifies the designers task and required knowledge base. Nexar requires little
or no experience with HDL or RTL source code to implement an FPGA design - opening up the market to designers who are familiar
with just board level design techniques. Nick Martin, Altium's founder and joint CEO discussed the benefits for EDA product
development associated with the selection of Verific's HDL Component Software, "We felt that it was crucial to provide strong
support for Verilog within Nexar. Rather than developing our own parsers and analyzers, we found that Verific's well-engineered
and reliable HDL Component Software was the right fit for our needs. We can focus on other aspects of Nexar, and strengthen
its position as the universal design system of choice for FPGA-based systems development."
APRIL 28th, 2005
PDF Solutions, Inc. (Nasdaq:PDFS), a design for manufacturing company,
reported that its revenue for its first quarter of 2005, ended March 31, 2005, reached a record $18.1 million, equivalent
to a 43 percent increase in revenue over the same quarter last year. For the first quarter, PDF's Integrated Design-To-Silicon-Yield
solutions accounted for $12.56 million in revenue, its yield software licenses for $3.45 million and gain share (a percentage
on semiconductor shipments from customers) was $2.1 million. Gain share revenue was more than double over last year’s
levels.
APRIL 27th, 2005
Apache Design Solutions, a private EDA company that focuses on dynamic
power design solutions, announced that its revenue has grown over 80 percent for its first quarter when compared to the same
quarter last year. The company also noted that its RedHawk-SDL tool, the company's lead product, has been used to produce
over 100 taped out chip designs from over 30 customers.
Andrew Yang, CEO of Apache commented on the design tool and the
tapeout milestone, "As the complexity of dynamic power integrity increases, our continuing technology advancements have enabled
us to keep pace with customers' needs and to gain their confidence in solving critical design issues. Achieving a major milestone
of 100 production tapeouts demonstrates the maturity of our solution and establishes RedHawk as the market leader in dynamic
power sign-off."
Apache has established subsidiary offices in Japan and Korea to
further expand its markets and support demand from around the world. The company also has sales and support offices in San
Diego, CA; Dallas, TX; Nice, France; and Bangalore, India.
APRIL 26th, 2005
Pointe to Deliver Design For Yield Platform
Pointe has joined the high-end of the Design for Yield (DFY) market.
The company has plans to deliver its DFY software in 2005. The software has capabilities to analyze and predict yield for
sub-100 nanometer designs at the multi-million gate level. The company to date has received Series A funding of about $10
million. Investors include Telos Venture Partners, US Venture Partners and Incubic LLC
Alex Alexanian, CEO of Ponte, talked about the need to correlate
vendor specific fab data with the actual planned chip design , "If you don't have good yields, you don't have a product to
sell. If you face yield problems at the manufacturing stage, you are late. These are the realities today. The semiconductor
industry today needs EDA tools that can provide visibility into yield problems and automatically fix these problems at the
design stage, before it is too late. Ponte's technology is an inevitable and effective solution for addressing yield challenges
at sub-130nm geometries." Translated the message implies that design engineers need to have vendor fab specific data at the
start of the algorithm or RTL level of the design process, not after layout or after prototype yield runs have been charged.
Jim Hogan, General Partner at Telos Venture Partners and Ponte board
member added, "The challenge of predicting and ensuring yields is one of the largest problems the semiconductor industry faces
at sub-130-nm process nodes," stated. Ponte is a company with the outstanding yield understanding, design expertise, team
and technology to solve this problem. They are in the right place with the right product and technology when customers are
looking for a solution to their yield issues."
APRIL 26th, 2005
Nassda, an accelerated transistor simulation company, announced
that its revenues increased 26 percent year-over-year and 10 percent sequentially. For the latest quarter ended March 31,
2005, revenues were $12.3 million.
Commenting on the increase and the company's acquisition by Synopsys
was Sang Wang, CEO of Nassda, "We are very proud to have achieved another quarter of sequential revenue growth and returned
to profitability with a 12% operating income, despite the substantial costs incurred related to the pending acquisition. Our
total cash, cash equivalents and short-term investments balances have also increased to $107.9 million at March 31, 2005,
Due to the pending acquisition, we are not providing any business outlook or guidance for the coming quarters."
APRIL 21, 2005
The MathWorks introduced SimPowerSystems 4, a design tool aimed
at a number of different industries. The tool comes complete with model libraries that include electric sources, electric
machinery, three phase components as well as standard passive components such as resistors, inductors and capacitors. Terry
Denery, Physical Modeling Product Marketing Manager at The MathWorks, implied that the tool has many uses and could be instrumental
for the design of renewable energy projects, "SimPowerSystems 4 leverages the power of Simulink to provide an efficient environment
for multidomain modeling and controller design. Now, engineers can model the generation, transmission, distribution, and consumption
of electrical power, as well as its conversion into mechanical power, all within Simulink."
TransEnergie Technologies Inc. developed the block libraries and
algorithms for SimPowerSystems. SimPowerSystems 4 sells for $3000.00.
APRIL 21, 2005
Fluent Inc., which focuses on design tools related to computationally
intensive fluid dynamics applications, has won part of a contact related to the U.S. Department of Energy's (DOE) clean coal
research projects, which in total consist of 32 projects valued at $62.4 million. As part of this $1.9 million contract, Fluent
heads a research team, which consists of both companies and research institutions: ALSTOM Power Inc., Aspen Technology Inc.,
and Carnegie Mellon University. This group plans to develop a "Software Framework for Advanced Power Plant Simulation," which
is to co simulate of the interaction of plant and energy generation equipment.
Lewis Collins, Fluent's Director of Funded Development indicated
that the project would advance power plant technology, "Fluent and its team are enthused about continuing the collaboration
with NETL that began in 2000 to advance the frontiers of virtual power plant design. We believe that the new software tools
developed through this project will significantly improve the ability of engineers to create innovative new concepts leading
to reduced plant life cycle costs, increased energy efficiency, and reduced environmental impacts."
The DOE Office of Fossil Energy's National Energy Technology Laboratory
(NETL) will manage the project. The DOE will contribute $1.9 million to the project and the other organizations involved will
provide matching funds.
APRIL 20th, 2005
Lattice Semiconductor Corporation (NASDAQ: LSCC) and Synplicity
Incorporated (NASDAQ: SYNP) entered into a development and marketing agreement that is intended to enhance the design and
performance of Lattice's FPGA chips. Joe Gianelli, Synplicity VP Business Development, said, "This agreement reflects our
unqualified commitment to deliver unprecedented device performance for Lattice FPGA products in our Synplify Pro software.
Performance is a hallmark of Synplicity's synthesis tools, and we are eager to continually expand and improve our support
for Lattice FPGAs."
APRIL 18th, 2005
Newfield Joins CoWare Partner Program
Newfield Technology, based in China, has joined CoWare's CoTeam partner
program as a service provider. Seyul Choe, Vice President, Asia Pacific at CoWare commented, “Advanced ESL tools need
the right IP models to be effective. Our ConvergenSC Model Library is the world's largest SystemC library, containing advanced
models for IP from a wide spectrum of vendors. As CoWare continues to expand its Asia-Pacific presence, we are pleased to
add Newfield Technology, an experienced and reliable local service provider, as a CoTeam partner. Its engineers are experts
in CoWare tools, and can provide fast simulation models and platforms for our processor and DSP partners."
APRIL 18th, 2005
Oki Electric Selects Forte's Area Optimized Synthesizer
Forte's Cynthesizer behavioral synthesis product, used in the front-end design flow
process to convert SystemC to RTL based chip designs, has been selected by Oki Electric Industry Co., Ltd. for the design
of its SoC chips. One of the reasons for the selection was the ability to achieve a silicon area metric that was competitive
with a handcrafted conversion. Kazuhiko Maki, Silicon Platform Design Department Senior Manager at Oki Electric, gave details,
"It has been a challenge to convert SystemC to RTL in a short period of time with low power consumption for our mobile application
designs. During our testing, Forte's Cynthesizer proved it produces a gate area that is equivalent to RTL conversion done
by hand, as well as reduce development time and power consumption. Going forward we will provide low power, high quality,
and short time-to-market products to our customers by using Cynthesizer in our system LSI development; we plan to incorporate
Cynthesizer into our standard design flow in the fiscal year ending March 2006.”
Brett Cline, Forte's Vice President of Customer Operations and Services commented
on the company's business relationship with Oki, "We are excited to have a leading semiconductor company such as Oki make
this next move in adopting Cynthesizer. We are especially pleased that Oki has already demonstrated Cynthesizer's quality
of results in production designs. This is further evidence of the growing momentum of both high level design and Cynthesizer
in today's IC design market." Forte specializes in design tools that enable the direct conversion of algorithms to either
ASICs, FPGAs or SoC custom chips.
APRIL 18th, 2005
Concept Engineering Slices Up SPICE Schematic to Reduce Design Time
Many engineers know the challenge it is to reduce simulation time of large chip designs.
and how it can effect overall design cycle time. One common obstacle, which increases simulation time, is the number of small
changes involved. This is compounded by the fact that after a small change in a design, often the entire circuit needs to
be simulated. Concept Engineering GmbH has a different approach to address this and related problems. Instead of importing
the entire circuit into an EDA design system after it is captured, why not just port portions of the design first. With Concept’s
SpiceVision PRO tool, engineers can select slices of a SPICE level schematic and export the slice into Cadence's Virtuoso
Schematic Editor Environment. Once ported, the slice can be optimized for a wide range of design parameters from silicon area
to power as the designer makes critical design changes. Azul Systems, which has designed multi-core processor-chip technology,
has used the SpiceVision PRO and the SKILL interface. Scott Sellers, Azul System's CTO, and co-founder validated the benefits
of using the tool, "The ability of the new interface to 'cookie cut' schematic fragments saves us from analyzing and debugging
a full circuit description. Therefore, we're now saving substantial simulation time."
Gerhard Angst, CEO of Concept Engineering talked further about the product, "Nanometer
technology is forcing design engineers to understand, optimize and debug their chip designs at the transistor-level. SpiceVision
PRO and the new SKILL interface help with this process."
Pat Dutrow, Director of the Cadence Connections program, also seemed positive about
Concept's product, "Our users wanted an efficient flow for transistor-level debugging. Concept Engineering has a complementary
debug solution that, when combined with the Virtuoso environment, helps address specific customer needs such as post-layout
transistor-level debugging and circuit fragment simulation. This is a good example of how Cadence uses an open collaboration
approach to deliver customer-focused solutions."
APRIL 18th, 2005
April is Busy Month for Magma
Design Automation
Magma Design Automation Inc. (Nasdaq:LAVA), has announced so far in April several
design wins and customers for its EDA tools. These include Oasis Semiconductor, Dolphin Technology and Sasken. This is on
top of an announcement with ARM about a joint low-power implementation design solution and ARM's adoption of Magma latest
Design for Test tool. Magma just introduced its BLAST DFT solution, which was chosen by ARM for yield improvement applications.
Several of Magma's customers praised the benefits of Magma's products. Mo Tamjidi,
CEO at Dolphin Technology stated, "Today's complex, high-density memories for nanometer processes require a thorough understanding
of the manufacturing process and defects to attain high yield. Blast DFT's automatic generation of timing constraints and
placement requirements, eases the integration of memories and associated test logic, and provides visibility into test problems
at the earliest stage. Dolphin's market-proven, high-performance, high-quality memories, combined with the well-integrated
test solution in Magma's RTL-to-GDSII flow, provide mutual customers high-yield and area-efficient memory implementation.
Magma's comprehensive test algorithms provide excellent coverage for new defects that occur in today's advanced processes
due to finer geometries."
Oasis Semiconductor, Inc, has now fully incorporated Magma's RTL-to-GDSII flow. "Since
we adopted Magma design tools over a year ago, we have been able to accelerate chip production schedules, lower costs and
raise clock rates," John Koger, CEO of Oasis confirmed and further substantiated Magma as a quality supplier, "In our high-volume,
customer-focused industry, realizing savings in areas such as die costs becomes significant. We have received top-notch support
from Magma and they have been committed to getting Oasis successfully up and running. The performance of the tool, combined
with their dedication, has reinforced our decision to choose Magma for the development of Oasis' chip designs for the demanding
and ever-changing semiconductor needs of the global multi-function peripherals market."
Sasken Communication Technologies Ltd., which Integrated Magma's Complete RTL-to-GDSII
Solution into its Design flow at Sasken's Semiconductor Business Unit, reported that the software offered significant reductions
in time to silicon and development costs. Shrikrishna Gokhale, Vice President of Sasken's Semiconductor Business Unit indicated
important reasons for the selection of Magm, "Sasken differentiates itself by being the only company in India
that works along the entire telecom value chain. We consider Magma a close collaborator that shares our philosophy of offering
our customers the ability to significantly lower design time and costs, while meeting specified requirements and achieving
the desired quality of results. By integrating Magma's RTL-to-GDSII tightly integrated design flow into our design methodology,
we have been able to reduce time to silicon by two to four months, even for complex communication designs, and with far fewer
engineers than before."
APRIL 13th, 2005
EVE Reports Record Growth - 380 Percent Year Over Year
Emulation and Verification Engineering (EVE), a verification based
EDA chip tools company, reports that for its fiscal year ended Thursday March 31, 2005 it doubled its customer base to 25
and had a growth rate of 380 percent year over year. EVE's lists of new customers includes numerous members of the top
tier of the IP core, IDM and fabless semiconductor market, not to mention those involved in the disk drive market: ARM Ltd.,
ATI Technologies Inc., Conexant Systems Inc., Flarion Technologies, Northrop Grumman Corporation, Renesas Technology
Corp., Rohm Electronics, Seagate Technology Inc., STMicroelectronics, Texas Instruments Inc., and Toshiba Corporation.
Luc Burgun, EVE's CEO, attributed the success in part to its
EDA design tool, ZeBu, "The groundswell of market acceptance confirms that our ZeBu platform is the only verification
solution on the market to address hardware/software integration and embedded software validation at more than five MHz on
designs exceeding 10 millions ASIC gates. We're upbeat and anticipate a great year of growth and profitability by further
augmenting our blue chip customer base
APRIL 13th, 2005
Sofjin's Custom EDA Operations Expand into the United States
Sofjin, a provider of custom EDA software and design flow solutions,
has moved into the Silicon Valley apparently after an overlooked growth market in the custom Design for Yield and Design for
Manufacturing markets. Nachiket Urdhwareshe, SoftJin's CEO explained the strategy and growth of the company, "Our goal
with respect to our new US office is to build on our past success, increase our market penetration and support the EDA software
development tool needs of our customers. We picked California because of Silicon Valley and our growing customer base in this
region."
Kalyan Patel, SoftJin's Business Development Manager in the United
States talked about the changes he sees in the EDA market, "We see a new inflection point in the EDA landscape with
customers requesting customized tools especially in the post-layout manufacturing area and for emerging programmable fabrics.
Our presence in the US will help us take advantage of these opportunities."
APRIL 12th, 2005
ChipMD, Design For Yield Company, to Tell its Story at Wescon
Yield has been and continues to be an important consideration for
integrated circuit companies. One of the reasons is that yield has a measurable effect on profit. ChipMD Inc., a Design For
Yield software tools company, is scheduled to give a talk at Wescon 2005, which begins on Wednesday, April 13th, 2005 at the
Santa Clara Convention Center in the Silicon Valley (Santa Clara, CA). Dale A. Pollek, CEO of ChipMD, will speak on Design
Optimization for Yield.
APRIL 11th, 2005
Zenasis Reveals Tier One Semiconductor Account for its Automated
Cell Design Tool
Zenasis Technologies, Inc., which offers automated chip design tools,
has reported that Agilent Technologies, a tier one semiconductor company in the United States, has used its tool to design
an image processing system-on-chip (SoC). The 90 nanometer chip designed with ZenTime included ChipWright's CWv16 DSP core.
a 2.5 Volt PLL, DMA, AMBA AHB bus bridge, bus monitor and arbiter.
ZenTime allowed Aglient to improve the timing performance of its
image-printing technology chip. According to Jay McDougal, IP Design Methodology Program Manager at Agilent's Imaging Solutions
Division, "With ZenTime, we saw significant timing improvement on one of our most challenging IP cores. Using ZenTime helps
Agilent maintain its SOC integration and performance leadership."
ZenTime is both an automated cell design tool and a timing optimization
tool, which is geared for standard cell designs. The tool performs timing optimization at the logic level, the transistor
level and the physical design level. The company indicates that its tool permits performance gains of 10 percent or more,
such that standard cell designs are able to achieve performance levels of custom chip designs, but without the associated
higher price.
APRIL 11th, 2005
Atmel Selects Prolific's Cell Layout Automation Software
A high quality automated cell library generation design tools has
helped Prolific Incorporated win Atmel Corp. as another account. According to Saeed Javadi, Director of ASIC Design
at Atmel, "We found through a competitive evaluation that ProGenesis was the right tool to help us satisfy our design requirements
and quickly produce the best possible libraries." Steve Jahnige, ASIC Engineering Manager at Atmel added, "ProGenesis
handles the advanced architectures we are developing. And Prolific has been very responsive in helping us achieve the results
we need."
Prolific's cell design automation tool, ProGenesis, automates the
engineering design intensive task of cell generation for integrated circuits. The tool is credited with the capability to
reduce cell library development time from weeks to days. Atmel uses ProGenesis for the creation of Standard Cell and Metal
Programmable libraries for the design of digital and mixed signal integrated circuits.
Prolific's other tier one semiconductor customers besides Atmel,
include AMD, Broadcom, NEC, and Samsung.
APRIL 11th, 2005
D'gipro, Post Sales Technical Support Company, to Distribute
Sequence's EDA Power Tools in India
Sequence Design, a company t
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