MARCH 31st, 2005
Magma Now in DRC Market With Two Hour Verfication Tool
With more beta shipments of its new design rule checking product
out the door, Magma Design Automation Inc. (Nasdaq:LAVA) is now a contender in the DRC market. As an apparent part of a long
range plan, the technology was developed through the acquisition of Mojave Design, which Magma acquired in 2004. The DRC software
and Magma's layout-versus-schematic (LVS) software was developed to address the latest semiconductor processes - presently
at the 90 nanometer and 65 nanometer levels. The software has also been targeted to meet a very aggressive two hour verification
time turn around schedule. Such a benchmark may give the few EDA companies in the DRC market something to think about.
Rajeev Madhavan, Magma's CEO, described the technology based market
opportunity, "We're very excited about the products that have resulted from the Mojave technology. To understand the opportunity
this represents for our company it's important to understand the philosophy behind Mojave. Fundamentally, the physics of design
have changed, and at 90 and 65 nanometers the effects of lithography and CMP (chemical mechanical polishing) now dominate
the physical verification rules that fabs use. Existing DRC/LVS tools -- architected as Dracula-compatible replacements in
the mid-1990s -- cannot handle these effects as effectively. We believe the capabilities of the Mojave technology in this
area have prompted the strong interest our customer base has shown."
The production release of the DRC product is scheduled in the summer
MARCH 30, 2005
RUTRONIK Selects Data I/O for Integrated Circuit Development
RUTRONIK, a design house based in Germany, has chosen Data I/O's
PS300 as an integrated circuit programming device for its operations. According to Thomas Rudel, Business Manager of Distribution
and Marketing at RUTRONIK, "With the PS300, we are able to program up to five million devices per year, and if required we
could increase that number easily within a few weeks. Our customers face tough competition. Now, RUTRONIK offers complete
customer service in device programming from a single source, allowing our customers to concentrate on their core competencies."
RUTRONIK has operations in several technology segments as a value
added reseller. The company lists these as component distribution, design consultation, custom ASIC design development, and
device programming services.
MARCH 29th, 2005
DAC Expected to Bring in 10,500 to Anaheim
The DAC, Design Automation Conference, which showcases the most
advanced electronic design products in the world, expects to see a crowd of about 10,000 this year. Among this crowd will
be those with an eye out for the EDA technology that will increase yield, reduce test time, eliminate design time, and overall
automate the design process. Will this year bring the ultimate design flow chart that goes from algorithm to cost-optimized
manufacturing in one step? Will this new product eliminate the need for the extensive and expensive steps of silicon design,
layout and back-end manufacturing analysis? And who has pushbutton EDA, that EDA tool that converts to the most-cost effective
medium (PLD, Gate Array, Structured Array, Standard Cell, and Custom), the most cost-effective vendor semiconductor process,
with an array of design specification constraint options.
MARCH 28th, 2005
UMC Selects Mentor Graphics' TestKompress Customer for 130
and 90 Nanometer Test
Mentor Graphics TestKompress Design for Test technology, which initially
came out in the market priced at around $2 million in 2001, will now be a part of UMC's silicon development solutions for
both 130 nanometer and 90 nanometer process technologies. The account win from one of the world's largest foundries
is evidence that the fabless, IDM and system customer base that UMC serves, have adopted Mentor's DFT tool. "Over the
years, UMC has been among the first to invest in technologies that help its customers manufacture reliable devices at the
lowest cost," said Robert Hum, Vice President and General Manager of the Design Verification and Test division for Mentor
Graphics. "UMC's decision to adopt TestKompress suggests that the tool is approaching critical mass as the industry standard
for embedded compression."
Ken Liou, Director of the IP Development and Design Support Division
at UMC noted, "TestKompress has shown that it can deliver outstanding test performance for complex devices while maintaining
reasonable cost. TestKompress adheres to our commitment to provide customers with services and methodologies for optimal silicon
development, and we are pleased to offer it to customers using our 130 and 90nm flows."
The patented TestKompression tool has been designed to expedite
test development time and reduce the factory test time per chip. Gregory K. Hinckley, president of Mentor Graphics noted
in early 2002, "The product can save major manufacturers hundreds of millions of dollars in test costs ........ We think
there is great potential for upside here in 2002." The CEO, Wally Rhines also projected that the TestKompression product was
expected to increase Mentor's DFT revenue by at least $20 million in 2002. Hitachi Semiconductor and Cisco Systems
were early adopters of Mentor Graphics' TestKompression software product
The test technology used for TestKompression is based on compression
technology. Compression technology embeds a compression circuit in the tester and a decompression circuit in the integrated
circuit. Data compression techniques also compress the actual test vector set, which reduces data storage requirements
from 10 to 1000 times. This results in reduced memory requirements on the tester, which permits a lower cost ATE machine to
Test compression permits the integrated circuit itself to generate
test vectors internally and automatically. For example, a test decompression circuit may generate anywhere from 10 to
1000 vectors for every test vector the test machine applies. This frees the tester to apply a test vector to another integrated
circuit to facilitate the testing of multiple integrated circuits at the same time on one tester machine - as
opposed to just one chip at a time.
MARCH 24th, 2005
Straatum Brings Preventive Yield Analysis Tools to Semiconductor Fab and Foundry
Processware Ltd., which has recently received funding from Intel Capital, ACT Venture Capital and Vision Capital, has introduced
its Imprint MX2 manufacturing fault detection system. This system, which extracts information in real-time from an array of
radio frequency and optical sensors located in the wafer fabrication line, allows wafer fabrication managers to quickly predict
where and when manufacturing induced product flaws are most likely to occur. The system, complete with a portable fault library,
has been designed to enable companies to alter process technology and locate semiconductor equipment that’s drifting
out of specification, before integrated circuit yield is affected. Such prediction capabilities are enhanced with the MX2’s
data mining features that allow for the quick classification of fault types and quick retrieval and analysis of the endless
flow of real-time data that a wafer fabrication plant generates and needs to collect and store.
MARCH 22nd, 2005
Agilent Ventures is a natural place to look for companies that want
funding for semiconductor test technology. And that's exactly where Pintail found part of the $7 million it secured in its
Series B venture capital round. Agilent Ventures, a business unit of Agilent Technologies, Inc. - a company with major operations
in semiconductor test equipment and electronic test instrumentation, participated in the round along with Austin Ventures,
Duchossois Technology Partners, IVF Ventures and STARTech Early Ventures.
Pintail was well received partly because of its performance in the
start-up phase and its list of world leading semiconductor customers. Phil Kirk of Duchossois Technology Partner noted, "Pintail
is distinguished by the companies it has engaged with during its development phase. Companies like Texas Instruments, Qualcomm,
STMicroelectronics and STATSChipPAC represent some of the most demanding semiconductor leaders in the world. The conflicting
needs for higher levels of quality in markets like automotive combined with lowering cost of test in all consumer products
are major challenges to the semiconductor industry. Pintail has developed innovative solutions to these challenges."
Pintail apparently has been able to win over customers because it
is able to save its clients significant amounts of money. Semiconductor test, because of the increased density and functionality
of integrated circuits has steadily risen over the years, and is something most CFOs at semiconductor companies would like
see substantially reduced. Pintail with its test operations software is able to reduce the amount of time it takes to test
a chip - in the order of 30 percent. This translates into over 30 percent per more chips per day through the factory - which
in some cases allows millions more chips per day to make it to the awaiting Fed Ex jet.
Pintail's software, because it is platform independent, and offers
real time data acquisition, and uses existing test equipment with only minor edits in test programs, allows these companies
to reduce test costs quickly without a significant capital investment - all of which pleases the company accountant. Taylor Scanlon, Pintail's president and CEO brought home the point, "Investment
in semiconductor test has taken a back seat to improving fab efficiency, especially in recent years. We are very pleased to
be backed by these world-class investors in our quest to bring true innovation to test. Our value proposition is obvious when
we hear that our customers are receiving significant benefits in every key area of concern in the test environment."
MARCH 16th, 2005
Knowlent Announces IP Interface Verification Design Tools - Completes Funding Round
Knowlent Corporation, a
relative newcomer to the EDA design tools market, has reported that its new high speed interface has seen rapid adoption.
With that news, the company has introduced Opal, an electrical verification platform for high-speed interface verification.
Specifically, the company announced Opal PCI Express EVP and Opal Serial ATA EVP. The company intends to release more design
tools for the verification of other standard bus interfaces.
The tool, which has been
designed for IP core applications, has won support from leading IP vendor, ARM. Callan Carpenter, ARM's Vice President and
General Manager of PHY Solutions stated, "The OPAL PCI Express EVP helped us save valuable time during the design of our 3G
PHY, and introduced a measure of independence between the design and verification process -- an important characteristic of
any good verification strategy. We anticipate working closely with Knowlent as they develop EVPs to support additional interface
standards." Others in the industry indicated that high speed interfaces, which see data rates above and beyond a GHz, are
a major design issue that needs to be more adequately addressed with specific design tools.
Knowlent also disclosed
that it completed its first round funding. The company however didn't release numbers. Investors included Denali Software
and AsiaTech Ventures.
MARCH 10th, 2005
a Design for Test Tool Company, Emerges at Design and Test Exposition
founded in 2003 and fresh with Series A funding it obtained in late 2004, has reported that it has been working with one of
the largest semiconductor manufacturers in Europe. The company through this working relationship plans to validate its Design for
Test (DFT) tools as the best on the market. DeFacto's management, which has a great deal of experience in the DFT arena, indicates
that as DFT demands increase, DFT will have to move much closer to the front-end of the chip design flow procedure. It is
within this framework that the company plans to compete with the well-known DFT companies, such as Synopsys. DeFacto Technologies
is based in Valence, France, with offices
in Grenoble, France and Palo Alto, CA, USA.
MARCH 10, 2005
Mathsoft, Developer of Engineering Productivity Software Secures $3.0 Million
Mathsoft, whose customers
include Bechtel, Intel, Lockheed Martin, NASA and Siemens has landed an additional $3 million investment from Edison Venture
fund, bringing Edison’s
total investment into the company to $6.5 Million.
Mathsoft offers the
Calculation Management Suite. The software package is intended to let engineers manage and document product development work
in progress. The tool assists engineers in the process of design reuse, such as IP core reuse for integrated circuit design,
auditing, oversight, publishing and collaboration. As well, the software can impose regulations to ensure the product development
procedure is done in compliance to set company, government and legal standards. Mathsoft indicates that the end result is
faster product development time.
Mathsoft software is
used by over ninety percent of the Fortune 1000 companies, 500 government agencies and 2,000 colleges and universities.
MARCH 8th, 2005
Sierra Design Automation Reports Rapidly Expanding Customer Base - Expands into Asia
and EuropeCiting a rapidly expanding customer base, Sierra Design Automation
Inc. has opened a sales and support office in Grenoble, France
and has announced distributors in the Asia Pacific. Sierra selected two distributors, Maojet Technology Corp. and Davan Tech
Co. Ltd. The distributors were selected for their capability to provide technical support and their relationships to ASIC
design companies and foundries n Taiwan and Korea respectively.
Sierra Design's physical synthesis design tools have
been developed to address chip designs which must be manufactured with state of the art semiconductor process technologies.
At this point in time, these are 90 nanometer and 65 nanometer based designs. Chips based on the latest semiconductor processes
in general command the highest average selling price and have the highest revenue growth rate in the overall chip market.
In Grenoble, France
Christophe Guittard will assume the position of General Manager Europe.
MARCH 7th, 2005
Xilinx FPGA Designer Base Rises to Over 200,000 Designers
For Many Reasons
With the release of
its 7.1i Integrated Software Environment (ISE) used for the development of Virtex and Spartan based FPGA designs, Xilinc's
software is expected to resolve a number of design issues that its user based of over 200,000 design engineers face in the
energy age. The design tool, which has been tailored for Linux-based design environments, has a number of power analysis tools built in. The XPower tool and the Xilinx Web Tools, which are used to analyze the
power consumption of your FPGA design, also can be used to illustrate the energy bill advantage Xilinx's 90 nm FPGAs have
over the competitions' 90 nm FPGAs. Xilinx indicates that the energy bill can be up to ten times less with its 90 nm FPGAs.
An important consideration for company's that want to sell their end-products into energy-conscience countries.
Xilinx also reports
that the new software release reduces FPGA real time verification time in the order of 50 percent. For this the simulator
makes use of its ChipScope Pro module, which can interface to Xilinx's in-house computer network and software.
The software also permits
rapid virtual prototyping of proposed architectures. In order to assess silicon areas, system electrical specifications of
a number of proposed block level chip designs, one can make use of the PlanAhead module incorporated into the ISE platform.
With this platform, one can determine quickly which architecture will have the best cost / performance ratio and which architecture
will be least likely to suffer from design reiterations or respins.
The ISE 7.1i design
software, with the above options and more, varies in price from $695 to $2495 depending on the configuration selected.
MARCH 7th, 2005
EDA Tool License From ATI Technologies
Tharas Systems, a provider
of hardware acceleration semiconductor design tools, has won a license from one of North America's largest fabless chip companies.
ATI Technologies selected Tharas's Hammer 100 accelerator for the verification of its next generation 3D graphics processors.
Greg Buchner, Vice President of Engineering at ATI Technologies pointed out that the Hammer 100 hardware accelerator is very
easy to use, offers extremely fast compile times and double digit acceleration when compared to software simulators.
Selects Verific's HDL to Chart Smart EDA Course
an EDA company that produces Library Smart tools for chip development, has chosen Verific Design Automation's hardware design
language (HDL) Component Software. Silicon Navigator will use the EDA software module for the development of its Open-Access
framework and engines.
Verific's module approach
to EDA tool development could represent an industry trend. The company reports that it has already licensed over 30,000 copies
of its EDA component software. Verific offers C++ source code-based SystemVerilog, Verilog and VHDL front ends. This includes
parsers, analyzers and general purpose hierarchical netlist databases.
MARCH 7th, 2005
VaST Puts Virtual
Prototype Design Tool on Market
VaST Systems Technology
Corporation now has available its Peripheral Device Builder. The new design tool, a virtual prototype tool, is used to quickly
design IP blocks such as interrupt controllers, DMAs, timers, and memory controllers. The company indicated that its customers
have reported reductions in model development time up to 75 percent with the product.
The Peripheral Device
Builder has been planned for general release on March 31, 2005. The design tool's one-year time-based node locked price has
been initially set at $25,000.
MARCH 7th, 2005
at DATE Show
Emulation and Verification
Engineering (EVE) will be one of the many companies exhibiting at the Design Automation and Test in Europe (DATE) 05 conference
this year. From March 8 to March 10, along with EVE, hundreds of other EDA companies will demonstrate their tools in Munich
Germany. These companies hope to convince the thousands of design engineers about design tool features offer everything from
reduced design time to lower silicon costs and higher yields.
EVE's approach revolves
around its architecture. For this, EVE offers ZeBu, for zero bugs. The ZeBu system is EVE's hardware assisted verification
platform. The system allows for the system developer to develop both hardware and software in a manner that is not hobbled
by the drawbacks of one-sided FPGA based verification system or the cost of emulators. ZeBu is said to offer the best of both
worlds. According to Eve, ZeBu is an easy to use system, which is able to quickly detect and locate errors, all with the performance
and price range of FPGA based hardware verification systems.
MARCH 4, 2005
Pulsic Limited's Layout Tool Designed to Conquer Silicon
Pulsic Limited, on an apparent roll with its analog and custom mixed
signal design tool, a high-speed shape based place and route tool, has opened up a new headquarters based in the heart of
Silicon Valley. The office is to be manned by Kirti Parmar, Applications Director for North America and Lee Williams, an applications
engineer from Pulsic's home office in the United Kingdom. Besides a series of design wins in Japan, Pulsic has already had
design wins in the United States. Noted high profile customers include On Semiconductor. In the United States, Pulsic has
an exclusive distribution agreement with Icthus Solutions.
In late February, Pulsic also announced that it had licensed its Lyric
physical synthesis technology to Elixent. The tool is to be used to reduce the time to port Elixent's D-Fabrix reconfigurable
algorithm processing technology to multiple silicon processes. Elixent's D-Fabrix array is produced from a library of custom
designed cells (at the transistor level). Pulsic's physical layout software will be used to design Elixent's cells and the
resultant cores. Elixent required a router that would enable the company to minimize power consumption and maximize speed
MARCH 4, 2005
India Wins Over Another EDA Company
This time its Synfora, the Application Engine Synthesis company, that
has adopted India at its home base for product development efforts. Synfora has announced that its India Engineering Center
in Bangalore is now open. There the staff develops technology which converts C based algorithms (software) to ultra fast hardware
ASIC solutions. The company focuses on standards based algorithms such as H.264, WMV and 3GPP. Specifically, the hardware
implementation of codecs is one specialized area that the design tool is well suited for. In addition to the staff already
there, Synfora expects to expand the team as it settles in.
MARCH 4, 2005
Celoxica Design Tool Expedites Conversion of C Algorithms
Celoxica now has available its programmable SoC prototyping and development
tool set. The platform, called the RC250 is an integrated hardware and software system design tool. Jim Smith, Director EDA
Vendor Relations for Altera emphasized that Altera and Celoxica have worked to provide a developmental design tool that would
give embedded systems developers the power to expedite the conversion of C-based software algorithms to hardware. The conversion
of software to hardware is driven by the demand for faster system performance. Hardware-based systems, in some applications,
can execute orders of magnitude faster than software-based systems.
Celoxica's RC250 includes a 9-million gate Altera Stratix II EP2S90
FPGA. The system development tool supports video applications, camera applications and Ethernet based applications. Graham
McKenzie, senior product marketing manager at Celoxica indicated that the RC250 is one of a series of boards, which support
high density reprogrammable logic chips, such as Altera's FPGA. The RC250 starts at $7,650.
MARCH 3, 2005
ARM and Synopsys Energy Manager Reduce Chip Power Consumption 60 Percent
ARM and Synopsys, as a result of a joint collaboration to produce lower power chip designs, have available a low-power
reference methodology that implements the ARM Intelligent Energy Manager (IEM). The
companies indicated that the IEM can reduce the power consumption of the ARM core by as much as 60 percent.
Actual power savings in a real chip design were underscored at Samsung. Sung Bae Park,
Vice President of Processor Architecture Lab at Samsung Electronics indicated that Samsung's work with both ARM and Synopsys
will expedite the development of the company’s next generation low-power devices for mobile applications. These mobile
devices are to be based on the ARM1176JZF-S and the IEM technology.
Mike Inglis, Executive Vice President of Marketing at ARM suggested that the dramatic power reduction gains were a
result of the integration and optimization of Artisan Physical IP within the ARM processor and Synopsys' integration of ARM and Artisan specific low-power design algorithms into its Galaxy Design Platform. He also indicated that ARM not only has the ability to offer low-power ARM cores to
its partners, but also low power IP solutions for entire SoCs.
Rich Goldman, Vice President of Strategic Alliances at Synopsys seemed to illusively imply that the success of the
power reduction optimization design flow was in part a result of the emphasis that Synopsys has placed on the integration
of power management technology into its Galaxy design tools for both ARM processor
specific designs and general SoC designs.
MARCH 3, 2005
Apache Design's RedHawk-EV Tool Used to Identify and Fix Low-Yield Chip Structures
Apache Design Solutions announced its next generation dynamic power analysis
and verification tool, RedHawk-EV. The tool, which is based on a vectorless dynamic
approach, identifies areas within the chip design that could reduce overall yield. The tool locates structures that have the
potential to result in excessive dynamic voltage drop, and voltage or current transients. As well, the tool also locates areas
that are over designed.
Shinichi Kozu, senior engineering manager, broadband LSI technology strategic business unit at NEC Electronics America,
Inc indicated that the tool enabled the company to identify potential power structure problem areas.
The EV tool also has the capability to fix wire related design problem areas. This is done, in part, through its automatic
non-uniform grid sizing feature. This feature can be used to lower the level of supply line noise in the design, which tends
to increase the yield levels and field reliability of semiconductors.