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FEBRUARY 26th, 2005
Oki Sees Better
Convergence and Correlation with Synopsys’ Tools
Synopsys, Inc. reported
that Oki Electric Co., Ltd. adopted its HSPICE MOS high voltage (HVMOS) model for the design of Oki's television driver system-on-a-chip
- a market Oki has placed significant emphasis into lately. Ichiro Yamamoto,
senior manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company indicated
that Synopsys’ model was chosen because of accurate correlation results and convergence properties. Other vendor's tools had differences between simulation and actual measured silicon of up to 30 percent.
The results with Synopsys HVMOS Aurora model extraction tool were, in stark contrast, within a few percent. This accuracy, Oki reports, greatly reduces the risk of respins. Another plus Oki noted was that engineers
were able to reduce the model parameter extraction time from several days to just two hours.
FEBRUARY 26th, 2005
Nascentric
Brings Out Super Accelerated SPICE Simulator
Nascentric, Inc. introduced
a super-accelerated SPICE level simulation tool that the company reports is 10 times faster than currently available accelerated
SPICE simulators. Nascentric also reports it has a number of other design tools in development that are transient aware (of
current or voltage pulses generated as a result of transistor switching action) – a major concern for designer whose
chips are based on the latest CMOS process technologies.
In order to obtain
super-accelerated, highly accurate simulations, Nascentric’ tool is based on a current model and a multiple-engine based
simulator. The current model allows for an accurate assessment of current density
in the interconnect of the design, which in turn allows for the accurate determination of IR drop, cross-coupling, electromigration
and switching leakage current. In order to further accelerate the simulation, the multiple-engine simulator dedicates a simulation
engine for the analysis of each of the distinct elements of the design: transistor, interconnect, cell and block.
FEBRUARY 26th, 2005
Anchor Semiconductor
Links Design to Manufacturing with UMC Account
Anchor Semiconductor
is now in the design for manufacturing (DFM) EDA market. Its Nanoscope tools were recently licensed to United Microelectronics,
one of the largest foundries in the world. Tools licensed include Anchor’s
Nanoscope PRV, DFP and YAM. These physical design tools permit designers to predict and compensate for optical proximity,
phase shift mask and other distortions that are introduced at the very last stages of manufacturing.
Dr. Long-Ching Yeh,
senior director of design support, System and Architecture Support Division at UMC indicated that the Nasoscope tools gives
design engineers the capability to predict and account for yield problems as a result of mask induced pattern distortions
early on in the design stage. Chip designers, with the advent of higher resolution process technologies, can no longer ignore
the effects of mask induced distortions on a chip’s electrical specifications. With quality DFM tools designers can
look ahead and see if the design will meet critical electrical specifications with mask induced distortions accounted for
– without implementing the lengthy front-to-back design flow.
FEBRUARY 26th,
2005
Silicon &
Software Systems Starts 65 nm Design with Cadence Encounter Platform
Cadence Design Systems
announced that Silicon & Software Systems (S3) has taped out multiple 90 nm designs based on its SoC Encounter digital
IC platform. Dermot Barry, general manager of the System IC Business Unit at S3 indicated that CeltIC and NanoRoute, two tools
in the design tool platform, permitted rapid timing and signal integrity closure. S3 says that it has started 15 designs based
on 90 nanometer technology, with volume ramp-up, and has begun two 65 nanometer designs. S3 has implemented a 4 million gate
design, with nine metal layers, and an ARM11 subsystem and clock speeds greater than 600 MHz.
FEBRUARY 16th, 2005
Ansoft Corporation reported that its revenue for the third quarter
of fiscal 2005 ended January 31, 2005 hit $17.4 million, up significantly from $14 million for the same quarter a year ago.
The company, which offers advanced chip design software for wireless applications, said that it expects revenue to also increase
in its fourth quarter. The company has developed a design flow, which allows for the modeling of inductors within integrated
circuits, critical for the development of the most advanced and lowest cost wireless electronic devices. UMC, one of world’s
largest foundries, has taken steps to accept designs based on the flow from its fabless customers.
FERBRUARY 16th, 2005
On Semiconductor Selects Sandwork’s EDA Tools to Reduce
Power Consumption
Sandwork Design, Inc. announced that its analog and mixed-signal circuit
design tools have been incorporated into ON Semiconductor’s power solutions design flow. ON Semiconductor is using Sandwork's
tools to debug Power Solutions chip designs. ON Semiconductor selected Sandwork's SPICE Explorer, WaveView Analyzer and CDS-Link.
Jo Hamid, Vice President R&D and Europe R&D Director at ON Semiconductor indicated that the selection of Sandwork’s
design tools was one more step the company has taken to reduce mixed-signal design time. Specifically he mentioned that time
savings were achieved with the WaveView Analyzer tool and simulation cycle times.
FEBRUARY 16th, 2005
With the advent of an RFID based supply chain, planners of RFID networks,
where merchandise must be tracked throughout the globe, have found that a need exists for a RFID network design tool package.
Such a tool, offered by iAnywhere Solutions, a subsidiary of Sybase, Inc., is now on the market. With such a tool, RFID network
planners can create a virtual network equipped with virtual readers, tags, barcode readers and merchandise and see how the
system might work in a real world environment - before the RFID network equipment is purchased!
Ideally, RFID network simulators would simulate the effect of noise
sources, such as electrical machinery, radio frequency interference, and take into account how different vendors tags interact
with each other and then receive a report on the reliability of the network. Hewlett-Packard announced some time ago plans
for a RFID test center. This test center mimics the harsh real-world industrial and transportation environment that RFID tags
and readers actually must work under. Hewlett-Packard has planned to tag its electronic products.
FEBRUARY 15th, 2005
Open-Silicon Selects LogicVision’s EDA Tools
FEBRAURY 15th, 2005
ATI Technologies Selects Cadence’s Palladium
Cadence Design Systems, Inc. has announced that ATI Technologies Inc.
selected its Palladium II acceleration/emulation system for the functional verification of ATI's digital television (DTV)
chip designs. David DiOrio, vice president of engineering at ATI Technologies, indicated that Palladium was the best choice
to reduce functional verification time.
According to Christopher Tice, senior vice president and general manager,
Verification Acceleration at Cadence, installations of the Palladium II EDA design tool has reached over 600 million gates
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FEBRUARY 14th, 2005
Emertec2
Fund Raises 20 Million Euro for Chips and Nano
Emertec
Gestion SA, based in France, plans to use its recent capital to invest in semiconductor
and nanotechnology companies. Investments markets mentioned include electronic design automation (EDA), chip
sets and RFID as well as advanced materials and processes. Investors in the 20 million Euro fund included AXA Private Equity,
CEA Valorization, CDC Entreprises, CNRS, Natexis Private Equity, and RBC Technology Ventures.
CNRS is a French research organization.
The
Emertec fund is expected to be dispersed to about 15 to 20 startups. Emertec plans to increase the fund size to about 40 million
Euros by the time fund closes. The fund traditionally has invested in European
based companies.
FEBRUARY
10th, 2005
Real Intent Closes $6.5 Million Round
Real
Intent, Inc., a provider of formal Assertion-Based Verification (ABV) software for the design of electronic circuits, has
closed a $6.5 million funding round. Investors in this round included Andy Bechtolsheim, co-founder of Sun Microsystems. Real
Intent’s design tools are used by over 30 electronics companies. These include Sun Microsystems, ATI Technologies, Agilent
Technologies, NEC Electronics, and nVidia.
FEBRUARY 9th, 2005
National Instruments Acquires Well-Known EDA Company
National
Instruments announced the acquisition of Electronics Workbench. Electronics Workbench’s tools have been widely accepted
in the university community in North America and Europe. The company’s tools are used to solve circuit simulation and board layout
problems.
FEBRUARY 8TH, 2005
EDA Company Offers Multimedia Focused Verification Tool
ProDesign, a company with
roots in layout design services, has continued its efforts to win in the electronic design automation market. The company
has just announced a design tool specifically tailored to meet the needs of multimedia chip designers. Called CHIPit Gold Edition Pro, the tool will be showcased at the DATE 2005 conference, scheduled for this
March.
ProDesign reports that
CHIPit Gold is a high-speed prototyping platform specifically designed for ASIC and SoC multimedia applications. The tool,
which can also be applied to IP core and algorithm verification, has been optimized for high-speed functional verification. ProDesign’s experience has been that multimedia ASIC and SoC designers have
a special need for very high-speed functional verification. The CHIPit Gold tool,
which is hardware assisted, has been designed to meet that requirement.
FEBRUARY 7, 2005
ArchPro Next Generation Design Approach Wins Funding
ArchPro Design Automation,
Inc. has scored another victory for India with Series A funding from Intel Capital. The
electronic design automation company apparently hit a nerve with its design tool strategy. The company plans to develop tools
for next generation 90 nanometer and 65 nanometer chip designs.
The design of the latest
chips with the latest process technologies has always been a high stakes game. Those
that bring out chips based on the latest process technologies, first, often win in the marketplace. However, new unforeseen
design problems associated with the latest process technologies, will often bring down even the best market plans. This leaves defeated chip companies pointing at the EDA tool
vendors.
Just as important though
is that EDA tools that address next generation process design problems, first, often gain market share quickly. This was brought
out in the last next generation process design tool race, when vendors that tackled crosstalk induced delays, first, were
well rewarded in the market place.
Although funding levels
for Series A were not revealed, participants in the funding besides Intel also included Sage Technology Ventures (STV) LLC.
The funds are expected to be used to help establish an R&D center in Bangalore, India, called PowerPlay Automation India Pty. ArchPro, based in Fremont
CA, has several requisitions posted for design positions in India.
FEBRUARY 7, 2005
Giga Scale Launches
EDA Tool Site
In other EDA news, Giga
Scale Integration Corporation announced that it has launched ChipEstimate.com, which designers can use to freely estimate
the cost of a design early on in the design cycle. MOSAID and Virtual Silicon’s intellectual property is bundled with
the InCyte design tool software
FEBRUARY 3, 2005
Mathematical IP Design Flow Reduces Nvidia’s Silicon Costs
Arithmatica, Inc., the silicon
math company, reported that it has integrated a front-end design flow for joint customers of Arithmatica and Cadence Design
Systems, Inc. NVidia, one of the world’s largest fabless graphic processor
companies, used the CellMath IP and design flow to obtain significant chip area reduction of floating point blocks. Arithmatica is an IP core company that is focused on the optimization of IP cores which are inherently
mathematically intensive.
FEBRUARY 3, 2005
India’s Technical Infrastructure Blossoms
Both Magma Design Automation
and Qualcomm have levied further designs on India.
Magma, in an apparent bid to grow more technical talent in India,
announced a partnership with International Institute of Information Technology-Hyderabad (IIIT-Hyderabad). The institute is expected to train semiconductor talent at the quasi-corporate educational organization
in the art of EDA based semiconductor design. These same researchers may one day make use of Magma’s design tools at
Qualcomm. Reports have it that Qualcomm will increase its employee count at its India
research centers by 200.
FEBRUARY 1, 2005
UMC and AnSoft Place Inductive Touch On RFCMOS Design Flow
Ansoft Corp. announced
along with United Microelectronics Corp (UMC) one of Taiwan’s
top chip foundries, the availability of one of the first parameterized spiral inductor design kits. The design kit links directly
between Ansoft’s RF design software and UMC’s process parameters. The inductor design kit is part of Ansoft and
UMC’s efforts to develop a completely qualified and tested electromagnetic based design flow for radio frequency based
CMOS chips. Such a flow permits the design of new high-growth market chips such as ultra wideband (UWB) radio chips.
FEBRUARY 1, 2005
Synopsys Wins Growing IP Core Account
Chipidea, based in Portugal,
has selected Synopsys’ Galaxy Design and Discovery Verification platforms. Chipidea is expected to use the design tools
for the development of its mixed signal and analog IP cores. Chipidea employs over 160 people and has plans to have over 250
employees in the year 2006.
FEBRUARY 1, 2004
Interface A Standard Rallies EDA Industry and Microsoft
The Interface A standard,
a Semiconductor Equipment and Materials International (SEMI) standard for the intense complicated operational information
generated from semiconductor manufacturing facilities has won friends in three industries. OSIsoft Inc. a process manufacturing
industry software company endorsed the standard. Microsoft and Asyst Technology, a semiconductor equipment company, also have
endorsed the standard. OSIsoft has plans to offer to semiconductor manufacturers a real-time software platform that displays,
the Interface A way, critical operational information.
In related Interface A
news, Cimetrix, a factory automation software company catering to the semiconductor and electronics industry, announced that
it has closed the placement of $2 million of common stock. One of Cimetrix's newest products, CIMPortal, is based on SEMI’s
Interface A equipment communications standards. Investors included Tsunami Network Partners Corporation, a company that has
ties in the Japanese high technology market.
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