JANUARY 31st, 2005
MatrixOne’s Software Grows With IP Market and IC Environmental Regulations
MatrixOne reported increased
its software license revenue 64 percent in its second fiscal quarter. The company’s total revenue for the quarter reached
$35.1 million. MatrixOne offers collaborative product lifecycle management solutions, which includes Intellectual Property
(IP) core reuses design management software (Synchronicity) and now MatrixOne Materials
Compliance Center software,
a software package intended to help technology companies navigate through a complex array of environmental regulations and
laws imposed in different continents and countries. MatrixOne names a few of
these directives. These include European End of Life Vehicle Directive (ELV), Restrictions on the use of certain Hazardous
Substances Directive (ROHS) and Waste Electrical and Electronic Equipment Directive (WEEE).
MatrixOne's design management,
IP and collaboration customers include a number of semiconductor and electronic companies: BAE Systems North America, Cypress
Semiconductor, Intel, LSI Logic, Motorola, Nortel Networks, Philips Semiconductor, PMC-Sierra, Inc., Sony Ericsson Mobile
Communications STMicroelectronics, QUALCOMM and Toshiba Corporation.
JANUARY 31, 2005
ARM Reports On EDA
ARM, which is primarily known
as an IP core business reported at the end of its latest quarter that it had begun to generate EDA license revenue. ARM’s
EDA business is a direct result of its acquisition of Adelante Technologies N.V., in 2003, the acquisition of Axys in 2004.
LG Electronics and Thomson both have licensed ARM’s OptimoDE embedded signal processing tool, which was obtained through
the acquisitions of Adelante and launched in August 2004. Thomson licensed the OptimoDE Data Engine in November 2004.
JANUARY 27th, 2005
Celoxica Obtains Multi-Year License From IC Giant
Toshiba, which recently reported a power management architecture that
drastically reduced power consumption for its Media Embedded Processor, has selected
Celoxica's C-Based Electronic System Level Design and Synthesis Technology for the development of designs based on
its Media Embedded Processor. The design software comes complete with a MeP developers
kit for the design and prototyping of MeP based system-on-chip (SoC) designs.
JANUARY 26th, 2005
On Semiconductor selected Vivecon Corporation’s capital investment
software to optimize wafer capacity utilization levels. The Integrated Power Group of On Semiconductor will use the
Legend Design Technology’s MSIM circuit simulator was selected
as the simulation engine for Magma Design Automation’s RTL-to-GDSII design flow.
Sierra Design Automation, Inc., won a multi-year, multi-license
contract from Fujitsu Microelectronics for its Sierra Pinnacle physical synthesis design tools. Fujitsu recently completed
a 11 million gate, 130 nm chip design with the tool.
Sharp Corp. said it devised a method to design chips in 40 percent
of the time required previously. The method uses the same design language to develop the chip hardware and software
together – eliminating several development steps related to on-chip hardware / software co-development.
JANUARY 25th, 2005
Power Optimization Design
Tools Win Market Share
Apache Design Solutions, a company that offers EDA tools that are used
to ensure that chip power is minimized, reported that its 2004 revenue tripled over 2003 levels. Furthermore the company announced
that its fourth quarter was its eighth consecutive record quarter.
JANUARY 25th, 2005
Power Management Architecture Cuts Power 40 Percent
The right tools and the right design strategy could be two keys to low-power chip design. Toshiba reported that it
reduced power consumption forty percent on its Media embedded Processor (MeP). Toshiba used a power management design architecture
that included dynamic voltage supply and frequency scaling design techniques. Toshiba says the power management architecture
can be applied to other system chip designs.
For the project, Toshiba used Synopsys’ tools, which could be a major part of thesuccess story. Synopsys over
the last year has made a considerable effort to build tools specifically to minimize power consumption and to enable power
optimization techniques. This has been a part of its chip yield enhancement program.
Minimized power tends to correlate with maximum chip yield.
JANUARY 19th, 2005
On Semiconductor Votes Pulsic EDA Router
Pulsic Ltd., a fairly young EDA company that entered the IC layout design market, despite the fact that Cadence Design
Systems completely dominated the market, appears to continue to make inroads. On Semiconductor is the latest company to license
Pulsic’s Lyric physical design solutions software. The software is planned
to be used for the placement and routing of On Semiconductor’s mixed signal chips.
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