Newfield Joins CoWare Partner Program

Newfield Technology, based in China, has joined CoWare's CoTeam partner program as a service provider. Seyul Choe, Vice President, Asia Pacific at CoWare commented, “Advanced ESL tools need the right IP models to be effective. Our ConvergenSC Model Library is the world's largest SystemC library, containing advanced models for IP from a wide spectrum of vendors. As CoWare continues to expand its Asia-Pacific presence, we are pleased to add Newfield Technology, an experienced and reliable local service provider, as a CoTeam partner. Its engineers are experts in CoWare tools, and can provide fast simulation models and platforms for our processor and DSP partners."

Oki Electric Selects Forte's Area Optimized Synthesizer

Forte's Cynthesizer behavioral synthesis product, used in the front-end design flow process to convert SystemC to RTL based chip designs, has been selected by Oki Electric Industry Co., Ltd. for the design of its SoC chips. One of the reasons for the selection was the ability to achieve a silicon area metric that was competitive with a handcrafted conversion. Kazuhiko Maki, Silicon Platform Design Department Senior Manager at Oki Electric, gave details, "It has been a challenge to convert SystemC to RTL in a short period of time with low power consumption for our mobile application designs. During our testing, Forte's Cynthesizer proved it produces a gate area that is equivalent to RTL conversion done by hand, as well as reduce development time and power consumption. Going forward we will provide low power, high quality, and short time-to-market products to our customers by using Cynthesizer in our system LSI development; we plan to incorporate Cynthesizer into our standard design flow in the fiscal year ending March 2006.”

Brett Cline, Forte's Vice President of Customer Operations and Services commented on the company's business relationship with Oki, "We are excited to have a leading semiconductor company such as Oki make this next move in adopting Cynthesizer. We are especially pleased that Oki has already demonstrated Cynthesizer's quality of results in production designs. This is further evidence of the growing momentum of both high level design and Cynthesizer in today's IC design market." Forte specializes in design tools that enable the direct conversion of algorithms to either ASICs, FPGAs or SoC custom chips.

Concept Engineering Slices Up SPICE Schematic to Reduce Design Time

Many engineers know the challenge it is to reduce simulation time of large chip designs. and how it can effect overall design cycle time. One common obstacle, which increases simulation time, is the number of small changes involved. This is compounded by the fact that after a small change in a design, often the entire circuit needs to be simulated. Concept Engineering GmbH has a different approach to address this and related problems. Instead of importing the entire circuit into an EDA design system after it is captured, why not just port portions of the design first. With Concept’s SpiceVision PRO tool, engineers can select slices of a SPICE level schematic and export the slice into Cadence's Virtuoso Schematic Editor Environment. Once ported, the slice can be optimized for a wide range of design parameters from silicon area to power as the designer makes critical design changes. Azul Systems, which has designed multi-core processor-chip technology, has used the SpiceVision PRO and the SKILL interface. Scott Sellers, Azul System's CTO, and co-founder validated the benefits of using the tool, "The ability of the new interface to 'cookie cut' schematic fragments saves us from analyzing and debugging a full circuit description. Therefore, we're now saving substantial simulation time."

Gerhard Angst, CEO of Concept Engineering talked further about the product, "Nanometer technology is forcing design engineers to understand, optimize and debug their chip designs at the transistor-level. SpiceVision PRO and the new SKILL interface help with this process."

Pat Dutrow, Director of the Cadence Connections program, also seemed positive about Concept's product, "Our users wanted an efficient flow for transistor-level debugging. Concept Engineering has a complementary debug solution that, when combined with the Virtuoso environment, helps address specific customer needs such as post-layout transistor-level debugging and circuit fragment simulation. This is a good example of how Cadence uses an open collaboration approach to deliver customer-focused solutions."

Tideline Lands $105 Million to Help Finance Software Purchases

Tideline Capital, a company that finances the purchase of software, has secured $105 million in funding for a software securitization facility. The funds are expected to help enable companies that must purchase software, such as expensive chip design software, to come up with the needed up-front capital often required. Tideline also announced that it has also raised $10 million in equity commitments as part of a Series A round. The funding for the securitization facility was made available through Wachovia Securities, which provided $100 million , and Comerica Bank, which contributed $5 million. The Series round participants included Voyager Capital, Odin Capital Group and Windingo Partners.

Mark McCall, a Director in Wachovia Securities Financial Institutions Corporate and Investment Banking Group commented on the new facility, "It has been difficult to securitize software receivables because software cannot be collateralized and is bound by intellectual property laws. Tideline Capital is filling a critical financing gap in the $200 billion software market. The firm's proven software finance expertise, comprehensive suite of services, and this unprecedented securitization facility combine to create a valuable and reliable new financing channel for the software industry."

Straatum Brings Preventive Yield Analysis Tools to Semiconductor Fab and Foundry Market

Straatum Processware Ltd., which has recently received funding from Intel Capital, ACT Venture Capital and Vision Capital, has introduced its Imprint MX2 manufacturing fault detection system. This system, which extracts information in real-time from an array of radio frequency and optical sensors located in the wafer fabrication line, allows wafer fabrication managers to quickly predict where and when manufacturing induced product flaws are most likely to occur. The system, complete with a portable fault library, has been designed to enable companies to alter process technology and locate semiconductor equipment that’s drifting out of specification, before integrated circuit yield is affected. Such prediction capabilities are enhanced with the MX2’s data mining features that allow for the quick classification of fault types and quick retrieval and analysis of the endless flow of real-time data that a wafer fabrication plant generates and needs to collect and store.

Knowlent Announces IP Interface Verification Design Tools - Completes Funding Round

Knowlent Corporation, a relative newcomer to the EDA design tools market, has reported that its new high speed interface has seen rapid adoption. With that news, the company has introduced Opal, an electrical verification platform for high-speed interface verification. Specifically, the company announced Opal PCI Express EVP and Opal Serial ATA EVP. The company intends to release more design tools for the verification of other standard bus interfaces.

The tool, which has been designed for IP core applications, has won support from leading IP vendor, ARM. Callan Carpenter, ARM's Vice President and General Manager of PHY Solutions stated, "The OPAL PCI Express EVP helped us save valuable time during the design of our 3G PHY, and introduced a measure of independence between the design and verification process -- an important characteristic of any good verification strategy. We anticipate working closely with Knowlent as they develop EVPs to support additional interface standards." Others in the industry indicated that high speed interfaces, which see data rates above and beyond a GHz, are a major design issue that needs to be more adequately addressed with specific design tools.

Knowlent also disclosed that it completed its first round funding. The company however didn't release numbers. Investors included Denali Software and AsiaTech Ventures.

DeFacto Technologies, a Design for Test Tool Company, Emerges at Design and Test Exposition

DeFacTo Technologies, founded in 2003 and fresh with Series A funding it obtained in late 2004, has reported that it has been working with one of the largest semiconductor manufacturers in Europe. The company through this working relationship plans to validate its Design for Test (DFT) tools as the best on the market. DeFacto's management, which has a great deal of experience in the DFT arena, indicates that as DFT demands increase, DFT will have to move much closer to the front-end of the chip design flow procedure. It is within this framework that the company plans to compete with the well-known DFT companies, such as Synopsys. DeFacto Technologies is based in Valence, France, with offices in Grenoble, France and Palo Alto, CA, USA.

Mathsoft, Developer of Engineering Productivity Software Secures $3.0 Million

Mathsoft, whose customers include Bechtel, Intel, Lockheed Martin, NASA and Siemens has landed an additional $3 million investment from Edison Venture fund, bringing Edison’s total investment into the company to $6.5 Million.

Mathsoft offers the Calculation Management Suite. The software package is intended to let engineers manage and document product development work in progress. The tool assists engineers in the process of design reuse, such as IP core reuse for integrated circuit design, auditing, oversight, publishing and collaboration. As well, the software can impose regulations to ensure the product development procedure is done in compliance to set company, government and legal standards. Mathsoft indicates that the end result is faster product development time.

Mathsoft software is used by over ninety percent of the Fortune 1000 companies, 500 government agencies and 2,000 colleges and universities.

Xilinx FPGA Designer Base Rises to Over 200,000 Designers For Many Reasons

With the release of its 7.1i Integrated Software Environment (ISE) used for the development of Virtex and Spartan based FPGA designs, Xilinc's software is expected to resolve a number of design issues that its user based of over 200,000 design engineers face in the energy age. The design tool, which has been tailored for Linux-based design environments, has a number of  power analysis tools built in. The XPower tool and the Xilinx Web Tools, which are used to analyze the power consumption of your FPGA design, also can be used to illustrate the energy bill advantage Xilinx's 90 nm FPGAs have over the competitions' 90 nm FPGAs. Xilinx indicates that the energy bill can be up to ten times less with its 90 nm FPGAs. An important consideration for company's that want to sell their end-products into energy-conscience countries.

Xilinx also reports that the new software release reduces FPGA real time verification time in the order of 50 percent. For this the simulator makes use of its ChipScope Pro module, which can interface to Xilinx's in-house computer network and software. 

The software also permits rapid virtual prototyping of proposed architectures. In order to assess silicon areas, system electrical specifications of a number of proposed block level chip designs, one can make use of the PlanAhead module incorporated into the ISE platform. With this platform, one can determine quickly which architecture will have the best cost / performance ratio and which architecture will be least likely to suffer from design reiterations or respins.

The ISE 7.1i design software, with the above options and more, varies in price from $695 to $2495 depending on the configuration selected.

Tharas Wins EDA Tool License From ATI Technologies

Tharas Systems, a provider of hardware acceleration semiconductor design tools, has won a license from one of North America's largest fabless chip companies. ATI Technologies selected Tharas's Hammer 100 accelerator for the verification of its next generation 3D graphics processors. Greg Buchner, Vice President of Engineering at ATI Technologies pointed out that the Hammer 100 hardware accelerator is very easy to use, offers extremely fast compile times and double digit acceleration when compared to software simulators.

VaST Puts Virtual Prototype Design Tool on Market

VaST Systems Technology Corporation now has available its Peripheral Device Builder. The new design tool, a virtual prototype tool, is used to quickly design IP blocks such as interrupt controllers, DMAs, timers, and memory controllers. The company indicated that its customers have reported reductions in model development time up to 75 percent with the product.

The Peripheral Device Builder has been planned for general release on March 31, 2005. The design tool's one-year time-based node locked price has been initially set at $25,000.

EVE Tempts at DATE Show

Emulation and Verification Engineering (EVE) will be one of the many companies exhibiting at the Design Automation and Test in Europe (DATE) 05 conference this year. From March 8 to March 10, along with EVE, hundreds of other EDA companies will demonstrate their tools in Munich Germany. These companies hope to convince the thousands of design engineers about design tool features offer everything from reduced design time to lower silicon costs and higher yields.

EVE's approach revolves around its architecture. For this, EVE offers ZeBu, for zero bugs. The ZeBu system is EVE's hardware assisted verification platform. The system allows for the system developer to develop both hardware and software in a manner that is not hobbled by the drawbacks of one-sided FPGA based verification system or the cost of emulators. ZeBu is said to offer the best of both worlds. According to Eve, ZeBu is an easy to use system, which is able to quickly detect and locate errors, all with the performance and price range of FPGA based hardware verification systems.

Pulsic Limited, on an apparent roll with its analog and custom mixed signal design tool, a high-speed shape based place and route tool, has opened up a new headquarters based in the heart of Silicon Valley. The office is to be manned by Kirti Parmar, Applications Director for North America and Lee Williams, an applications engineer from Pulsic's home office in the United Kingdom. Besides a series of design wins in Japan, Pulsic has already had design wins in the United States. Noted high profile customers include On Semiconductor. In the United States, Pulsic has an exclusive distribution agreement with Icthus Solutions.

In late February, Pulsic also announced that it had licensed its Lyric physical synthesis technology to Elixent. The tool is to be used to reduce the time to port Elixent's D-Fabrix reconfigurable algorithm processing technology to multiple silicon processes. Elixent's D-Fabrix array is produced from a library of custom designed cells (at the transistor level). Pulsic's physical layout software will be used to design Elixent's cells and the resultant cores. Elixent required a router that would enable the company to minimize power consumption and maximize speed performance.

India Wins Over Another EDA Company

This time its Synfora, the Application Engine Synthesis company, that has adopted India at its home base for product development efforts. Synfora has announced that its India Engineering Center in Bangalore is now open. There the staff develops technology which converts C based algorithms (software) to ultra fast hardware ASIC solutions. The company focuses on standards based algorithms such as H.264, WMV and 3GPP. Specifically, the hardware implementation of codecs is one specialized area that the design tool is well suited for. In addition to the staff already there, Synfora expects to expand the team as it settles in.

Celoxica now has available its programmable SoC prototyping and development tool set. The platform, called the RC250 is an integrated hardware and software system design tool. Jim Smith, Director EDA Vendor Relations for Altera emphasized that Altera and Celoxica have worked to provide a developmental design tool that would give embedded systems developers the power to expedite the conversion of C-based software algorithms to hardware. The conversion of software to hardware is driven by the demand for faster system performance. Hardware-based systems, in some applications, can execute orders of magnitude faster than software-based systems.

Celoxica's RC250 includes a 9-million gate Altera Stratix II EP2S90 FPGA. The system development tool supports video applications, camera applications and Ethernet based applications. Graham McKenzie, senior product marketing manager at Celoxica indicated that the RC250 is one of a series of boards, which support high density reprogrammable logic chips, such as Altera's FPGA. The RC250 starts at $7,650.

ARM and Synopsys Energy Manager Reduce Chip Power Consumption 60 Percent

ARM and Synopsys, as a result of a joint collaboration to produce lower power chip designs, have available a low-power reference methodology that implements the ARM Intelligent Energy Manager (IEM).  The companies indicated that the IEM can reduce the power consumption of the ARM core by as much as 60 percent. 

Actual power savings in a real chip design were underscored at Samsung. Sung Bae Park, Vice President of Processor Architecture Lab at Samsung Electronics indicated that Samsung's work with both ARM and Synopsys will expedite the development of the company’s next generation low-power devices for mobile applications. These mobile devices are to be based on the ARM1176JZF-S and the IEM technology. 

Mike Inglis, Executive Vice President of Marketing at ARM suggested that the dramatic power reduction gains were a result of the integration and optimization of Artisan Physical IP within the ARM processor and Synopsys' integration of  ARM and Artisan specific low-power design algorithms into its Galaxy Design Platform.  He also indicated that ARM not only has the ability to offer low-power ARM cores to its partners, but also low power IP solutions for entire SoCs.

Rich Goldman, Vice President of Strategic Alliances at Synopsys seemed to illusively imply that the success of the power reduction optimization design flow was in part a result of the emphasis that Synopsys has placed on the integration of  power management technology into its Galaxy design tools for both ARM processor specific designs and general SoC designs.

Apache Design's RedHawk-EV Tool Used to Identify and Fix Low-Yield Chip Structures

Apache Design Solutions announced its  next generation dynamic power analysis and verification tool, RedHawk-EV.  The tool, which is based on a vectorless dynamic approach, identifies areas within the chip design that could reduce overall yield. The tool locates structures that have the potential to result in excessive dynamic voltage drop, and voltage or current transients. As well, the tool also locates areas that are over designed.

Shinichi Kozu, senior engineering manager, broadband LSI technology strategic business unit at NEC Electronics America, Inc indicated that the tool enabled the company to identify potential power structure problem areas.

The EV tool also has the capability to fix wire related design problem areas. This is done, in part, through its automatic non-uniform grid sizing feature. This feature can be used to lower the level of supply line noise in the design, which tends to increase the yield levels and field reliability of semiconductors.  

Oki Sees Better Convergence and Correlation with Synopsys’ Tools

Synopsys, Inc. reported that Oki Electric Co., Ltd. adopted its HSPICE MOS high voltage (HVMOS) model for the design of Oki's television driver system-on-a-chip - a market Oki has placed significant emphasis into lately.  Ichiro Yamamoto, senior manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company indicated that Synopsys’ model was chosen because of accurate correlation results and convergence properties.   Other vendor's tools had differences between simulation and actual measured silicon of up to 30 percent. The results with Synopsys HVMOS Aurora model extraction tool were, in stark contrast, within a few percent.  This accuracy, Oki reports, greatly reduces the risk of respins. Another plus Oki noted was that engineers were able to reduce the model parameter extraction time from several days to just two hours.

Nascentric Brings Out Super Accelerated SPICE Simulator

Nascentric, Inc. introduced a super-accelerated SPICE level simulation tool that the company reports is 10 times faster than currently available accelerated SPICE simulators. Nascentric also reports it has a number of other design tools in development that are transient aware (of current or voltage pulses generated as a result of transistor switching action) – a major concern for designer whose chips are based on the latest CMOS process technologies.

In order to obtain super-accelerated, highly accurate simulations, Nascentric’ tool is based on a current model and a multiple-engine based simulator.  The current model allows for an accurate assessment of current density in the interconnect of the design, which in turn allows for the accurate determination of IR drop, cross-coupling, electromigration and switching leakage current. In order to further accelerate the simulation, the multiple-engine simulator dedicates a simulation engine for the analysis of each of the distinct elements of the design: transistor, interconnect, cell and block.

Anchor Semiconductor Links Design to Manufacturing with UMC Account

Anchor Semiconductor is now in the design for manufacturing (DFM) EDA market. Its Nanoscope tools were recently licensed to United Microelectronics, one of the largest foundries in the world.  Tools licensed include Anchor’s Nanoscope PRV, DFP and YAM. These physical design tools permit designers to predict and compensate for optical proximity, phase shift mask and other distortions that are introduced at the very last stages of manufacturing.

Dr. Long-Ching Yeh, senior director of design support, System and Architecture Support Division at UMC indicated that the Nasoscope tools gives design engineers the capability to predict and account for yield problems as a result of mask induced pattern distortions early on in the design stage. Chip designers, with the advent of higher resolution process technologies, can no longer ignore the effects of mask induced distortions on a chip’s electrical specifications. With quality DFM tools designers can look ahead and see if the design will meet critical electrical specifications with mask induced distortions accounted for – without implementing the lengthy front-to-back design flow.

Ansoft Corporation reported that its revenue for the third quarter of fiscal 2005 ended January 31, 2005 hit $17.4 million, up significantly from $14 million for the same quarter a year ago. The company, which offers advanced chip design software for wireless applications, said that it expects revenue to also increase in its fourth quarter. The company has developed a design flow, which allows for the modeling of inductors within integrated circuits, critical for the development of the most advanced and lowest cost wireless electronic devices. UMC, one of world’s largest foundries, has taken steps to accept designs based on the flow from its fabless customers.

Sandwork Design, Inc. announced that its analog and mixed-signal circuit design tools have been incorporated into ON Semiconductor’s power solutions design flow. ON Semiconductor is using Sandwork's tools to debug Power Solutions chip designs. ON Semiconductor selected Sandwork's SPICE Explorer, WaveView Analyzer and CDS-Link. Jo Hamid, Vice President R&D and Europe R&D Director at ON Semiconductor indicated that the selection of Sandwork’s design tools was one more step the company has taken to reduce mixed-signal design time. Specifically he mentioned that time savings were achieved with the WaveView Analyzer tool and simulation cycle times.

With the advent of an RFID based supply chain, planners of RFID networks, where merchandise must be tracked throughout the globe, have found that a need exists for a RFID network design tool package. Such a tool, offered by iAnywhere Solutions, a subsidiary of Sybase, Inc., is now on the market. With such a tool, RFID network planners can create a virtual network equipped with virtual readers, tags, barcode readers and merchandise and see how the system might work in a real world environment - before the RFID network equipment is purchased!

Ideally, RFID network simulators would simulate the effect of noise sources, such as electrical machinery, radio frequency interference, and take into account how different vendors tags interact with each other and then receive a report on the reliability of the network. Hewlett-Packard announced some time ago plans for a RFID test center. This test center mimics the harsh real-world industrial and transportation environment that RFID tags and readers actually must work under. Hewlett-Packard has planned to tag its electronic products.

Open-Silicon, Inc, a fabless ASIC company has adopted LogicVision’s embedded memory-test and repair-analysis technology. Request More Information - Specify Company, Product, Etc.

National Instruments Acquires Well-Known EDA Company

National Instruments announced the acquisition of Electronics Workbench. Electronics Workbench’s tools have been widely accepted in the university community in North America and Europe. The company’s tools are used to solve circuit simulation and board layout problems.

EDA Company Offers Multimedia Focused Verification Tool

ProDesign, a company with roots in layout design services, has continued its efforts to win in the electronic design automation market. The company has just announced a design tool specifically tailored to meet the needs of multimedia chip designers.  Called CHIPit Gold Edition Pro, the tool will be showcased at the DATE 2005 conference, scheduled for this March.

ProDesign reports that CHIPit Gold is a high-speed prototyping platform specifically designed for ASIC and SoC multimedia applications. The tool, which can also be applied to IP core and algorithm verification, has been optimized for high-speed functional verification.  ProDesign’s experience has been that multimedia ASIC and SoC designers have a special need for very high-speed functional verification. The  CHIPit Gold tool, which is hardware assisted, has been designed to meet that requirement.

Giga Scale Launches EDA Tool Site

In other EDA news, Giga Scale Integration Corporation announced that it has launched ChipEstimate.com, which designers can use to freely estimate the cost of a design early on in the design cycle. MOSAID and Virtual Silicon’s intellectual property is bundled with the InCyte design tool software

MatrixOne’s Software Grows With IP Market and IC Environmental Regulations

MatrixOne reported increased its software license revenue 64 percent in its second fiscal quarter. The company’s total revenue for the quarter reached $35.1 million. MatrixOne offers collaborative product lifecycle management solutions, which includes Intellectual Property (IP) core reuses design management software (Synchronicity) and now MatrixOne Materials Compliance Center software, a software package intended to help technology companies navigate through a complex array of environmental regulations and laws imposed in different continents and countries.  MatrixOne names a few of these directives. These include European End of Life Vehicle Directive (ELV), Restrictions on the use of certain Hazardous Substances Directive (ROHS) and Waste Electrical and Electronic Equipment Directive (WEEE).

MatrixOne's design management, IP and collaboration customers include a number of semiconductor and electronic companies: BAE Systems North America, Cypress Semiconductor, Intel, LSI Logic, Motorola, Nortel Networks, Philips Semiconductor, PMC-Sierra, Inc., Sony Ericsson Mobile Communications STMicroelectronics, QUALCOMM and Toshiba Corporation.

Celoxica Obtains Multi-Year License From IC Giant

Toshiba, which recently  reported a power management architecture that drastically reduced power consumption for its Media Embedded Processor, has selected  Celoxica's C-Based Electronic System Level Design and Synthesis Technology for the development of designs based on its Media Embedded Processor.  The design software comes complete with a MeP developers kit for the design and prototyping of MeP based system-on-chip (SoC) designs.

Power Optimization Design Tools Win Market Share

Apache Design Solutions, a company that offers EDA tools that are used to ensure that chip power is minimized, reported that its 2004 revenue tripled over 2003 levels. Furthermore the company announced that its fourth quarter was its eighth consecutive record quarter.

On Semiconductor Votes Pulsic EDA Router Technology In

Pulsic Ltd., a fairly young EDA company that entered the IC layout design market, despite the fact that Cadence Design Systems completely dominated the market, appears to continue to make inroads. On Semiconductor is the latest company to license Pulsic’s Lyric physical design solutions software.  The software is planned to be used for the placement and routing of On Semiconductor’s mixed signal chips.