In a joint announcement, Cadence Design Systems, Inc. (NYSE:CDN) (NASDAQ:CDN) and Fujitsu Microelectronics America, Inc. (FMA) reported that FMA will ship initial production volumes of a structured ASIC that was designed with Cadence’s Encounter design tool. The ASIC is scheduled to ship this month, in August. The design flow used was based on FMA’s AccelArray family of structured ASICs.
 
Noboru Yokota, senior director of engineering at FMA indicated that Cadence’s tool was used because it could implement standard ASICs as well as structured ASICs, "We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs. This very complicated design, which FMA completed with AccelArray Giga Frame, implements about 1.4 million instances of cell."

The design Mr. Yokota refers to contains 3.5 million logic gates, as well as SRAM memory, a register file and a 12-channel 3.125G SERDES. The SERDES is intended to make the design compatible with high-end servers.

The Fujitsu AccelArray Giga platform, based on years of Fujitsu’s ASIC experience, is intended for mid-volume markets. Fujitsu indicates that the Giga Platform expedites the ASIC design process. Specifically, the use of the structured array can reduce physical design time related to Design for Test (DFT) insertion, as well as analysis time related to the power grid, clock tree synthesis and simultaneous switching outputs. The Giga platform also includes pre-diffused G-PHY macro cells, which enable 75 Gbps of full-duplex SERDES bandwidth.