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Cubic Wafer Prepares for Growth

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September 14th, 2005
 
Cubic Wafer Prepares for Growth – New 3D Die and Wafer Stack Technology offers Cost and Size Reduction for Consumer Electronic Products
 
Cubic Wafer, in anticipation of growth form its 3D stacking technology, has relocated its headquarters to Austin, Texas and naming Ed Healy, chief executive officer and Abhay Misra as vice president of operations and engineering. According to Russ Johnsen, chairman of the board of Cubic Wafer. "The benefit of having a management team in place with the skills Ed and Abhay bring is their ability to immediately capitalize on our technology by implementing a strategic plan for achieving a revenue stream in the short term without losing sight of our long-term objectives. We are confident Cubic Wafer is positioned to create an industry shift to transform and advance the integration possibilities of the semiconductor industry."
 
Cubic Wafer indicates that its process technology for the vertical integration of silicon die will offer solutions for consumer electronic products such as cameras, PCs printers, and wireless devices.
The two new members of Cubic’s team plan to establish partnerships with chip companies to enable dramatic reduction of chip production costs. Specifically targeted are high volume Asian foundries, assembly and packaging companies.

Cubic Wafer’s process technology is used to fuse integrated circuits at the die or wafer level. The company bills the technology as “The chip becomes the board.”  This technology can be  used to bond together chips manufactured with different process technologies such as analog and digital CMOS processes with over a million communication contacts per square centimeter. These contacts or bonds are reported to be one-thousand time shorter than the IO connections found on today’s horizontal chips. The reduction of IO length portends to lower power and higher speed chip solutions.  The company also indicates that it solution combines the best advantages of system-in-packaging and system-on-chip design methodologies to obtain a very cost-effective, smaller, faster, and lower power solution.

 
Copyright 2004, 2005, Mark C. Stansberry, All Rights Reserved
 
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