WWW.PERFECTDISPLAY.COM - Where Technology Converges

SEMICONDUCTOR ASIC NEWS - STRUCTURED AND PROGRAMMABLE

Field Programmable Gate Arrays, Field Programmable Analog Arrays,  Field Programmable Object Arrays, PLDs, Structured ASICS

Home | Beauty and Health | EDA News | Medical Technology Journal | Micromachnes and Nanomachines Database | Semiconductor Evening News | World Energy Technololgy | NAVIGATION | E-MAGAZINES | E-DIRECTORIES | NEWSWIRES | PRESENTATIONS | BUSINESS INTELLIGENCE | Rebuilding New Orleans | Story Book Corner - Coloring Books and More | SEARCH THE SITE | IC Companies By Alphabet - S | NFL Football | List Your Company Profile | Halloween Fun | Greeting Cards

>

>

>

August 11th, 2005
 
Fujitsu to Ship Structured ASICS - Designed with Cadence Tools 

In a joint announcement, Cadence Design Systems, Inc. (NYSE:CDN) (NASDAQ:CDN) and Fujitsu Microelectronics America, Inc. (FMA) reported that FMA will ship initial production volumes of a structured ASIC that was designed with Cadence’s Encounter design tool. The ASIC is scheduled to ship this month, in August. The design flow used was based on FMA’s AccelArray family of structured ASICs.
 
Noboru Yokota, senior director of engineering at FMA indicated that Cadence’s tool was used because it could implement standard ASICs as well as structured ASICs, "We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs. This very complicated design, which FMA completed with AccelArray Giga Frame, implements about 1.4 million instances of cell."

The design Mr. Yokota refers to contains 3.5 million logic gates, as well as SRAM memory, a register file and a 12-channel 3.125G SERDES. The SERDES is intended to make the design compatible with high-end servers.

The Fujitsu AccelArray Giga platform, based on years of Fujitsu’s ASIC experience, is intended for mid-volume markets. Fujitsu indicates that the Giga Platform expedites the ASIC design process. Specifically, the use of the structured array can reduce physical design time related to Design for Test (DFT) insertion, as well as analysis time related to the power grid, clock tree synthesis and simultaneous switching outputs. The Giga platform also includes pre-diffused G-PHY macro cells, which enable 75 Gbps of full-duplex SERDES bandwidth.

 August 8th, 2005
 
MathStar Files for $32 Million IPO

MathStar, Inc., a company that has developed a new type of programmable chip called the Field Programmable Object Array or FPOA, has filed a registration statement with the United States Securities and Exchange Commission (SEC) for an Initial Public Offering (IPO) to raise up to $32 million. The company has initially proposed to offer 4,000,000 shares of common stock. The company anticipates that the stock will fetch a price of somewhere between $6 and $8 per share, for a total of $32 million on the high end. The company plans to use the net proceeds for research and development, sales force expansion, marketing and to pay its 8 percent convertible promissory notes. Feltl and Company will manage the offering.

 
Copyright 2004, 2005, Mark C. Stansberry, All Rights Reserved
 
TERMS OF USE
 
The publisher of this web site does not certify that the information contained on this web site is 100 percent accurate. Use of this web site requires that the reader release the publisher from all liability that may result from the reliance of information on this web site. The publisher suggests that readers verify any information contained on this web site with three or more other reference sources, as well as directly with any company(s) mentioned. Please report any errors or omissions to marketing@perfectdisplay.com.
 
The site may include words, or phrases that are specific trademarks of companies mentioned.