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August 25th, 2005
Analog Devices Offering Design Tool to Speed Clock Network Design
IC companies aren’t waiting around for EDA companies to offer design tools optimized to produce systems based
on their own chips. Filling a need to offer design tools that get the most system performance for system designs based on its
own products, Analog Devices has a design tool called ADIsimCLK, a tool used to simplify and expedite clock design as well
as to ensure that designers are able to reduce system clock jitter to the lowest possible level.
According to Kevin Kattmann, product line director, High Speed Converters, Analog Devices, "Use of low-phase-noise, low-jitter
clock ICs reduces overall noise in a signal path. However, optimizing clock solutions can be painstaking and time consuming.
The ADIsimCLK tool was created to simplify the clock distribution design process by allowing customers to analyze and test
critical timing circuits before committing to hardware, reducing risk and shortening development time. The ICs introduced
today help customers who need a better way to distribute low jitter clocks across a crowded PCB to multiple sub-circuits.
Customers can now route common clock frequencies up to 1.6 GHz to the AD9513/14/15, which perform divides, phase offsets,
and delays in close proximity to the circuits needing clocks. The small packages allow customers to save on board space and
cost, while improving their overall system performance."
Besides the ability of ADIsimCLK to simulate jitter of less than 1 picosecond RMS, it can also simulate phase noise less
than dBc/Hz. ADIsimCLK has been optimized to for loop filter design with Analog Devices' family of low jitter clock ICs without
the need to build a hardware prototype. The tool permits a variety of different types of simulations, which include frequency
response and timing diagram analysis, in addition to allowing the direct substitution of different voltage controller oscillators
to see the effect on the overall clock tree design.
The AD9513, AD9514 and AD9515 can reduce additive jitter levels to less than 300 femtoseconds rms, or additive jitter
of 225 femtoseconds up to 1.6 GHz. The 3-channel AD9513 and AD9514 are priced at $5.95 per unit in quantities of 1000. The
2-channel AD9515 is priced at $4.75 per unit in 1,000-piece quantities.
August 23rd, 2005
IDT Introduces Notebook Clocks – Reduces Power 50 Percent
Integrated Device Technology, Inc., (NASDAQ:IDTI), has introduced a series of PC clock devices that
the company reports reduces power consumption 50 percent over the company’s previous clock chips. According
to Tom Kao, director of marketing, IDT PC clock product line, "Notebook PC manufacturers have issued a clear call to action
to all their suppliers, requesting that they reduce power consumption across the board. Today's announcement underscores our
continued efforts to deliver industry-leading PC clock solutions to the market. By lowering the power consumption of our PC
clock devices by up to 50 percent, we are doing our part to reduce overall power in computing systems, while ultimately contributing
to the greater cause of providing consumers with a better user experience."
The company indicated that the advancement was a result of power reduction
technology related to the I/O of the devices. I/O (Input / Output) cells are used to connect the small transistors within
the chip to the package lead that connects the circuit to the printed circuit board traces. Because of the need to drive the
high capacitance loads of the package and PC board traces, I/O circuits within the chip consist of larger transistors and
are responsible for a disproportionate share of power consumption in integrated circuits.
The new low-power PC clocks have been designed for present day and future
Intel laptop microprocessors such as the Centrino. The clock chips are priced from 99 cents in quantities of 10,000.
AUGUST 11th, 2005
X-EMI, a fabless semiconductor company focused on electromagnetic
interference reduction, introduced its XM1001 transceiver at EMC 2005, a trade show held in Chicago, Illinois. The new transceiver
is the first of several that X-EMI has planned intended to reduce electromagnetic interference in electronic systems. The
demonstration at the show illustrates how the XM1001 reduces EMI 25 dB without added shielding, without design changes and
with no added jitter.
The XM1001, which is reported as in the sampling stage, is a clock
generator / clock transceiver chip, which according to the company can reduce EMI radiation levels over 25 dB based on what
the company calls Optimized Spectral Diffusion (OSD). Larry Woodson, CEO of X-EMI, indicated that the 25 dB number is
conservative, "We tested the XM1001 both internally, and externally in an independent lab environment, where the results were
actually greater than 25 dB of EMI reduction. However, we know that real life does not often imitate a lab environment, no
matter how careful we are to replicate it. We also know that our best endorsements come from outside experts and our customers
who are currently sampling the product. We feel comfortable in saying that designers and developers of electronics systems
will not approach EMI reduction in the same way again, and product marketers will no longer fear a time-to-market delay due
to emission compliance. This small chip could save a multi-million dollar product launch, and spread across several electronics
industries, that translates into billions of dollars saved."
Dr. Howard Johnson, who is considered an EMI industry expert, (http://www.sigcon.com/), was very positive about X-EMI’s new chip, "I have often fantasized
about clock transceiver technology that combines zero jitter and zero emissions. Today, X-EMI brought my dream one step closer
to reality. OSD integrates the best aspects of spread spectrum modulation with reliable digital system design practice. The
XM1001 produces clock signals that are full-sized, with great signal quality, and low jitter, but the radiation simply vanishes.
If radiation from your clock was a problem before, it isn't a problem any more. "
The XM1001 is also classified as a stand-alone oscillator and / or
frequency synthesizer that offers both differential or single-ended input and output, in addition to supporting PCI Express
and SATA applications. The chip’s specifications permit operation up to 250 MHz, a cycle to cycle jitter of less than
25 picoseconds, and a plus or minus 300 parts per million clock output frequency accuracy
With the product announcement, X-EMI also said that it has achieved
its product and funding goals for 2005, noting that it raised $13 million in a Series A round in July. As far as its
marketing efforts, the company reported that it has entered into agreement with Magellan Discovery and Nova Marketing in regards
to the marketing and distribution of their product in the Pan Asian and United States market, respectively.
August 9th, 2005
One of the major stumbling blocks for wireless electronics has been
the integration of the necessary RF oscillation components into silicon. Left off chip, these components add to the power
consumption of everything wireless from cell phones to Bluetooth enabled headsets.
The goal of the FP6 project, coordinated by IMEC, one of the leading
R&D organizations in Europe and the world, is to demonstrate an oscillator that can be integrated with silicon so as to
give every silicon chip integrated wireless connectivity at low cost.
Such an achievement would have significant implications. One such
implication is that many of the IO used on chips would no longer be needed and that massively parallel wireless digital FPGA
based multiprocessor systems could be created without wires or complex wired PC boards. Besides the architectural implications
of wireless processors, semiconductor companies would also have a potential solution for the expensive test problems associated
with chips that have hundreds of IOs. On a product applications level, an all wireless chip world would
offer a path to the elimination of wired Internet connections. Currently complete cellular internet connections are expensive;
necessitating wireless WiFi connections to PC based wired connections.
The approach that is being tried through the European Union's FP6
project is referred to as "Tunable Nano-Magnetic Oscillators for integrated transceiver applications" or TUNAMOS-project.
A nano-magnetic oscillator is tuned with a magnetic field or current as opposed to today’s oscillators, which require
an inductive or capacitive element to be tuned to generate a specific frequency. IMEC reports that the tuning range
of the nano-magnetic oscillator is in the range of 5 to 40 GHz. The organization also reports that the Quality (Q) of
the nano-magnetic oscillator has been measured at 18,000.
IMEC indicates that the nano-oscillator is a candidate suitable
for silicon integration and like all integrated circuits can be scaled downward as process technology evolves towards lower
and lower feature lengths – lowering the cost and improving the performance of the oscillator at each process node.
Besides IMEC, other involved in the TUNAMOS-project include STMicroelectronics,
UPS Universite Paris Sud and UFSD University of Sheffield. The project was initially launched in June of 2005 and is expected
to be completed within three years.
AUGUST 5th, 2005
Crystal oscillators, used to provide the master clock for many electronic
systems and chips, will see silicon as a competitor with On Semiconductor’s phase locked loop (PLL) circuit. ON
Semiconductor (NASDAQ: ONNN) has introduced the NB4N507A, which it reports as the first of a series of PLL chips designed
to specifically replace crystal oscillators for clock generation applications.
On Semiconductor has overcome two obstacles in the design of a silicon
based crystal replacement circuit. One is the cost and the other is the jitter specification, a specification that crystal
oscillators often easily outscore silicon on. On Semiconductor though reports that the accuracy of its PLL chip is 100 parts
per million (ppm), making the NB4N507A, according to On Semiconductor, “a preferable alternative to crystal oscillators
with similar stability.” The chip has a maximum root mean square (RMS) period jitter of less than 10 picoseconds. Bill Schromm, ON Semiconductor vice president and general manager of High Performance
Analog products, emphasized that the chip offered a superior alternative to crystal, "ON Semiconductor has developed a superior
silicon replacement solution for crystal oscillators. Utilizing a fully differential bipolar design methodology, ON Semiconductor's
NB4N507A PLL offers inherent noise immunity and full industrial temperature operation not obtainable by competitive CMOS PLL
clock generation devices."
Despite the potential silicon inroads into the crystal market, crystal
makers do not have to worry that their markets will go away soon. The NB4N507A, for one, does not address the high end for
digital chips. It is only capable of generating a clock signal ranging from 50 MHz to 200 MHz, and even at that it still requires
an inexpensive reference crystal. However, On Semiconductor points to other benefits of the silicon clock generator. One is
that the silicon lead time for such a part is for the most part much less than the lead time for equivalent crystals, and
that the silicon design offers more design flexibility – such as the ability to more readily change the master clock
frequency.
On Semiconductor also sites lower costs, on the order of a fraction
of the cost of a crystal. Specifically, the company quoted a price of $1.50 for the NB4N507A in 1,000 unit quantities. The
chip is packaged in a 16-pin SOIC.
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