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September 13th, 2005
Accelrys Introduces Nanotechnology Design Tool
Accelrys, Inc. (NASDAQ:ACCL) has introduced ONETEP, a nanodesign tool developed in conjunction
with the members of the Accelrys Nanotechnology Consortium. The consortium was formed to expedite the development of nanomaterials
and nanodevices. Mark J. Emkjer, CEO of Accelrys commented on ONETEP broad applicability, "With the launch of the ONETEP software
solution, the first deliverable against our target of increased accuracy, capabilities and performance across a broad range
of nanoscale applications, the Consortium is well on its way to fulfilling the promise of furthering the rational design of
nanomaterials and nanodevices. With the Consortium's membership continuing to grow, we are well positioned to develop novel
technologies that meet the needs of the scientists and engineers who are participating in and building the nanotech industry."
Noting the value of nanodevice simulation was Bob Daniels, vice
president of research and development at Lyondell Chemical Company, "We recognize the potential value of molecular modeling
as a means of reducing the cost of new materials research. Accelrys has created a collaborative nanotechnology forum where
Lyondell's needs for specific modeling capabilities are being satisfied. We will deploy these tools to real-world problems
to provide solutions that create a strategic advantage in an increasingly complex and competitive market."
Specific
applications for the ONETEP nanosimulator include nanotubes, mixed bio-materials systems and oxide nanoparticles.
The consortium, which just added seven members, includes organizations
from industry, the academic world and government. The new members include Kyoto University, Millennium Chemicals (A Lyondell
Company), R.J. Mears, CSIC of Spain and PPG Industries. Other members include Corning Incorporated, Fujitsu, e2v Technologies,
Imperial College, Uppsala University, Johnson Matthey, Schenectady International, Fraunhofer IFAM, Fraunhofer IZM and the
Japan Advanced Institute of Science and Technology.
September 9th, 2005
Texas Instruments to Offer Educational Webcast
about TINA Spice Simulation Program
In an effort to provide high-quality technical support for SPICE
based circuit simulation, Texas Instruments has scheduled a live Analog eLab Webcast entitled, "Designing with TINA-TI." The
webcast, presented with Avnet Electronics Marketing Division, will offer an online discussion and demonstration of TINA-TI’s
circuit simulation software. The webcast, complete with on-board analog design experts, is expected to commence at 11:00 a.m.
Central Daylight Time on September 14th. Topics covered include the use of the tool and a lab session centered on the simulation
and accuracy of simulations based on TI’s macromodels.
The TINA-TI design tool is available free at Texas Instrument’s
web site.
September 8th, 2005
Applied Wave Research Acquires APLAC – Expands European and RF IC Market Share
Applied Wave Research, Inc., known for its wireless tools used in the design of electronics systems and chips, has acquired
APLAC Solutions Oy (APLAC). With the acquisition, Applied Wave has acquired APLAC’s RF design tool technology, which
has been used to design over 30 percent of all of Nokia’s mobile phone RF integrated circuits. According to Applied,
the merger was driven by customer demand to further integrate APLAC’s foundry based circuit simulation technology with
Applied’s AWR Design Environment technology. James Spoto, President of Applied spoke about the integration of the two
companies’ technology, "APLAC Solutions is a world class R&D organization with compelling expertise in simulation
and modeling. The integration of our R&D teams along with our combined EDA strengths will accelerate AWR's already rapid
rise in the RF EDA space."
The acquisition has given Applied a major research and development center in Europe, opening the way for further penetration
into Europe’s market. The newly merged company now has process design kits for Europe’s three largest semiconductor
companies: Infineon Technologies, Philips Semiconductor, and STMicroelectronics.
The company noted that beta copies of Applied’s AWR Microwave Office and APLAC RF design tool are now available.
September 1st, 2005
Sequence Signs KPIT – Order through Indian Distributor
Sequence Design, one of the largest private integrated circuit Electronic Design Automation companies, has obtained another
customer in India. The IC design consulting, KPIT Cummins Info Systems, was the first company in India signed by Sequence’s
distributor there, D’gipro. KPIT chose Sequence’s Columbus-AMS RLC parasitic extraction tool. Vic Kulkarni, Sequence
CEO indicated that KPIT was a beacon for India’s chip market, "KPIT Cummins is the first Indian customer signed by D'gipro
since we named them our exclusive distributor there and marks a major milestone in Sequence's India operations. KPIT's focus
on complex designs gives us a sense of where the future of chip design is going for the Indian design community, and we look
forward to working closely with them through our India Center of Excellence."
Praveen Acharya, vice president, VLSI, KPIT Cummins gave leading edge reasons for the selection of Sequence’s products,
"KPIT Cummins has been providing leading edge 90nm based design services to its STAR customers. It is necessary for our valued
clients to get the benefits of our advanced design flow and design quality at the most competitive cost. The adoption of Sequence
Columbus-AMS into our design flow has further strengthened our services portfolio for key customers."
KPIT Cummins is a broad based company. In India alone it has a software development center in Pune and a VLSI design
center in Bangalore. The VLSI design center provides SoC Design and Verification, Analog and Mixed Signal Design, Physical
Implementation and other chip design services, which range from system architecture development to test.
KPIT other subsidiaries are located in the United States, Europe, the Middle East and Japan. Its technology market focus
includes automotive, industrial automation and semiconductor solutions. The company is also involved in the banking, financial
services and insurance fields. KPIT reports that it has had a growth rate of 77 percent CAGR over the last three years.
August 26th, 2005
Analog Devices Offering Design Tool to Speed Clock Network Design
IC companies aren’t waiting around for EDA companies to offer design tools optimized to produce systems based
on their own chips. Filling a need to offer design tools that get the most system performance for system designs based on its
own products, Analog Devices has a design tool called ADIsimCLK, a tool used to simplify and expedite clock design as well
as to ensure that designers are able to reduce system clock jitter to the lowest possible level.
According to Kevin Kattmann, product line director, High Speed Converters, Analog Devices, "Use of low-phase-noise, low-jitter
clock ICs reduces overall noise in a signal path. However, optimizing clock solutions can be painstaking and time consuming.
The ADIsimCLK tool was created to simplify the clock distribution design process by allowing customers to analyze and test
critical timing circuits before committing to hardware, reducing risk and shortening development time. The ICs introduced
today help customers who need a better way to distribute low jitter clocks across a crowded PCB to multiple sub-circuits.
Customers can now route common clock frequencies up to 1.6 GHz to the AD9513/14/15, which perform divides, phase offsets,
and delays in close proximity to the circuits needing clocks. The small packages allow customers to save on board space and
cost, while improving their overall system performance."
Besides the ability of ADIsimCLK to simulate jitter of less than 1 picosecond RMS, it can also simulate phase noise less
than dBc/Hz. ADIsimCLK has been optimized to for loop filter design with Analog Devices' family of low jitter clock ICs without
the need to build a hardware prototype. The tool permits a variety of different types of simulations, which include frequency
response and timing diagram analysis, in addition to allowing the direct substitution of different voltage controller oscillators
to see the effect on the overall clock tree design.
The AD9513, AD9514 and AD9515 can reduce additive jitter levels to less than 300 femtoseconds rms, or additive jitter
of 225 femtoseconds up to 1.6 GHz. The 3-channel AD9513 and AD9514 are priced at $5.95 per unit in quantities of 1000. The
2-channel AD9515 is priced at $4.75 per unit in 1,000-piece quantities.
August 25th, 2005
HiSilicon Completes Communications Chip
Design With Cadence Encounter
Cadence Design Systems, Inc. (NYSE:CDN) and Semiconductor Manufacturing
International Corporation (SMIC) (NYSE:SMI) reported that HiSilicon Technologies Co., Ltd., formerly Huawei Technologies'
ASIC Design Center , completed a communications chip design with Cadence’s Encounter digital chip design platform based
on SMIC’s integrated circuit manufacturing rules. According to Ai Wei, executive vice president of HiSilicon, "Using
the Cadence Encounter platform and SMIC's process, we designed a high-performance device for China's competitive communications
market. The collaboration with Cadence and SMIC helped to reduce the time and costs required to develop a product that meets
our customers' specifications. We look forward to using the new Encounter-based reference flow, which should help us deliver
cost-sensitive, low-power designs."
Shenzhen HiSilicon Semiconductor Co., Ltd., originally founded in
1991, has over 100 patents and possesses IP as a result of hundreds of internal chip designs. The company reports that it
also invests over $20 million annually in R&D, which has resulted in designs at the 0.18 micron and 0.13 micron level
that have over 50 million logic gates.
August 24th, 2005
Interra’s EDA Building Blocks Integrated into Carbon Design’s EDA Chip Prototype
System
Interra has integrated its Verilog-Cheetah and VHDL-Jaguar analyzers into Carbon Design System’s virtual system
prototyping (VSP) solution, an EDA design tool used to quickly determine the feasibility of different design architectures
with different IP cores, and different hardware and software models. Carbon Design indicated that Interra’s EDA tool
building blocks expedited the development time of its VSP tool. "Interra's expertise in hardware description languages accelerated
our time-to-market with proven Verilog and VHDL language front-ends," noted Alan Swahn, Vice President of Marketing and Business
Development at Carbon Design Systems. "Interra's technology, integration services, and Beacon test suites were a valuable
asset to our product development," he added.
Interra Systems EDA tool development blocks are for front-end applications. They have been designed into over 40 EDA
and System-on-Chip companies, which include Atrenta, Axis, Carbon, CoWare, Magma, Mentor Graphics, and Synopsys.
Central to Carbon’s Virtual Silicon Prototype or VSP tool is the ability to execute on a desktop billions of instruction
cycles and boot from embedded operating systems. The tool enables the parallel development of both hardware and software,
without the need for silicon prototypes.
August 23rd, 2005
As a result of studies that involve the interaction of silicon and molecules, researchers at Purdue University
have developed what may be considered the first simulator for nanoelectronic systems. That tool, referred to as a nanotech
simulator, is based on electric conductivity models of atoms and molecules. The researchers on the project indicate that the
simulator has been developed to determine the electrical interaction of molecules and atoms so that silicon based technology
can be integrated to form molecular and atomic silicon-based electronic systems.
These systems are not expected to utilize metal contacts, but instead rely on electronic flow between silicon and
a variety of different molecules. The initial research centers around Buckyballs, which measure about 10 atoms wide, or about
one nanometer in width. The interaction of Buckyballs, which are molecules that are comprised of carbon atoms, were modeled
within the simulator to see their effect on electrical flow when connected to silicon atoms. The research has shown that the
electrical current flow changes when a different chemical bond is used to connect the Buckyballs with the silicon atoms. The
simulation results were correlated with actual measured results. The researchers confirmed that the simulated conductance
and voltage results matched that of the simulator.
In order to study the conductivity of different molecules, one can also substitute other molecules for the Buckyballs
and then perform simulations with the nanosimulator. This enables those in the semiconductor and biochip market to find out
more about the conductivity of silicon when connected with different bonds with different types of molecules –
expediting the development of biological based electronic silicon systems.
August 23rd, 2005
The National Science Foundation (NSF), based in the United States,
has awarded $150 million for the operation of the Extensible Terascale Facility, also referred to as the TeraGrid. The distributed
computer system links together supercomputers and other computational resources together to give researchers the capability
to analyze vast and highly complex problems in genetics, nanotechnology and engineering that require extensive computer analysis
time. According to Deborah Crawford, the acting director of NSF’s Office of Cyberinfrastructure, one of the goals is
to eventually open TeraGrid directly to a scientists and engineers, such that these scientists and engineers can access the
TeraGrid from web portals with their desktop computers.
Supercomputer based organizations that are involved in the project
include The University of Chicago Argonne National Laboratory, Indiana University, the National Center for Supercomputing
Applications, the U.S. Department of Energy Oak Ridge National Laboratory, the Pittsburgh Supercomputing Center; Purdue
University, the San Diego Supercomputer Center, and the Texas Advanced Computing Center
Crawford considers the project critical for the advancement of science,
"We fully expect TeraGrid to catalyze the next generation of scientific discoveries. Simply put, breakthrough science and
engineering depends on a first-class cyberinfrastructure."
Guy Almes, NSF program manager , who oversees the project, noted
that the project would bring together researchers, "TeraGrid enables scientists and engineers to both be more productive in
their research and education as well as enjoy doing this work with cutting-edge tools while working closely with peers around
the world."
August 22, 2005
Ansoft Corporation (NASDAQ:ANST) for its first quarter of fiscal
2006 ended July 31, 2005 reported revenue of $14.8 million, up 17 percent from $12.7 million it reported for the same period
last year. Ansoft’s license revenue for the quarter was $6.82 million compared to $6.17 million. Its service and other
revenue came in at $7.97 million compared to $6.51 million for the same period last year.
Indicating future revenue growth was Nicholas Csendes, Ansoft's
President and CEO, "We had an excellent first quarter with strong growth in revenues and earnings. For the balance of the
fiscal year, we expect continued revenue growth of around 10-15% with earnings increasing around 25% over the last fiscal
year."
Ansoft provides a variety of electronic design software for a number
of different applications. These include integrated circuits, printed circuit boards, automotive electronic systems, cellular
phones, and power electronics.
August 22nd, 2005
SELEX Sensors and Airborne Systems (SELEX S&AS), based in the
United Kingdom has entered into a three year agreement with Agilen Technologies EDA unit to use the company’s Advanced
Design System (ADS) electronic design automation software. The agreement incudes technical support, training and ADS licenses.
SELEX will use the design tools for the design of RF and microwave electronic circuits.
One of the reasons the company selected the software was because
of Agilent’s on-site support. According to Melvin Simpson, engineering director for SELEX S&AS, "We selected
Agilent's ADS as the cornerstone of our microwave design toolset because of Agilent's superior simulation technology and flexible
options for access to this software, along with its on-site support and training. The complete software and support package
allows us to maximize the return on our design tools investment."
August 17th, 2005
Aldec Signs Site License with Renasas for 10,000 HDL Simulators – Slated
for Vietnam Unit
Aldec, Inc. has entered into an agreement with Renasas, one of Japan’s major chip companies, to supply 10,000
Rivera HDL Simulators. The HDL simulators, often used for the design of ASICs and FPGAs, will be installed at Renasas Design
Vietnam Co. Ltd. Aldec indicated that Renasas purchased the Rivera-SNA (Simulator for Networking Applications) for the parallel
verification of system level chips based on Renasas’ microprocessors.
The term of the virtual license is three years with an option to renew. As well, Aldec will provide on-site technical
support throughout the design lifecycle, which will be reviewed quarterly. The agreement also alludes to potential further
purchases of other Aldec’s products such as its hardware acceleration and co-verification products.
Tsuneo Sato, President of Renesas Design Viet Nam Co., Ltd. indicated that working with Aldec was strategic for development
of its next generation technology, "We are pleased to be working with Aldec and look forward to a successful partnership to
address the verification demand of our next generation devices. Our best strategy for developing new technology is to work
very closely with a company such as Aldec who is dedicated to providing solutions to our verification problems."
Renasas is one of the first chip companies noted to establish a design base in Vietnam. Because of a low cost of living,
Vietnam could very well become another popular alternative in the overseas design labor market. Besides the native population,
the large population of Vietnamese engineers in the United States could become another human resource chip companies tap to
establish their technology bases in Vietnam.
August 11th, 2005
Fujitsu to Ship Structured ASICS - Designed with Cadence Tools
In a joint announcement, Cadence Design Systems, Inc. (NYSE:CDN) (NASDAQ:CDN) and Fujitsu Microelectronics America, Inc.
(FMA) reported that FMA will ship initial production volumes of a structured ASIC that was designed with Cadence’s Encounter
design tool. The ASIC is scheduled to ship this month, in August. The design flow used was based on FMA’s AccelArray
family of structured ASICs.
Noboru Yokota, senior director of engineering at FMA indicated that Cadence’s
tool was used because it could implement standard ASICs as well as structured ASICs, "We chose the Encounter platform as the
netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility
in implementing standard ASIC and structured ASIC designs. This very complicated design, which FMA completed with AccelArray
Giga Frame, implements about 1.4 million instances of cell."
The design Mr. Yokota refers to contains 3.5 million logic gates, as well as SRAM memory, a register file and a 12-channel
3.125G SERDES. The SERDES is intended to make the design compatible with high-end servers.
The Fujitsu AccelArray Giga platform, based on years of Fujitsu’s ASIC experience, is intended for mid-volume markets.
Fujitsu indicates that the Giga Platform expedites the ASIC design process. Specifically, the use of the structured array
can reduce physical design time related to Design for Test (DFT) insertion, as well as analysis time related to the power
grid, clock tree synthesis and simultaneous switching outputs. The Giga platform also includes pre-diffused G-PHY macro cells,
which enable 75 Gbps of full-duplex SERDES bandwidth.
August 10th, 2005
Mentor Graphics Reports Revenue – Revises Guidance
For the three months ended June 30, 2005, Mentor Graphics Corporation (NASDAQ:MENT) one of the
three leading Electronic Design Automation companies, reported revenues of $154.8 million. That’s down from $169.6 million
reported for the same period ended June 30, 2004. The company also reported results for the latest six month period, also
ended June 30, 2005. For the six month period, revenues were down, $319.2 million compared to the same period last year,
which came in at $334.0 million.
The company reported that its System and Software revenue also dropped
for the quarter, $81.4 million compared to $98.1 million for the same quarter last year. Service and support revenue however
increased on a year-over-year quarterly basis to $73.5 million from $71.6 million for the same period quarter last year.
Mentor breaks down its revenue into two major components, System and Software, and Service and Support.
Mentor Graphics also revised guidance. It now projects that its third
quarter revenue will fall somewhere between $160 million and $165 million, while for the entire 2005 year, Mentor projects
revenue to be between $700 million and $705 million. For the 2006 year, Mentor sees growth in the order of 7 percent to 8
percent over the 2005 year, or somewhere in the order of $755 million.
Commenting on the financials was Walden C. Rhines, CEO of Mentor
Graphics. He noted that bookings doubled in some areas and that FPGA products did well during the quarter, "Despite
weaker bookings, there were many signs of an improved business climate in the quarter. New customer logo additions were up
nearly 20% over the second quarter of 2004, up both worldwide, and in every region. Bookings from new customers doubled from
the year ago quarter, as well. During the quarter, we saw good bookings growth in most of our new and emerging products. Automotive
electrical system design products more than doubled over the second quarter of 2004, and design data management, Catapult
C Synthesis, embedded and FPGA tools all did well during the quarter."
Gregory K. Hinckley, president of Mentor Graphics, besides expressed
confidence in the company’s Calibre design for manufacturing tools, as well as reflected on the effect of currencies
on the company’s financials, "During the quarter, currency moved in a positive direction for Mentor. A strengthening
Yen and a weakening Euro are both helpful for Mentor. While the first half was weak, we are still confident that key products
like the Calibre family will deliver in the second half." He also commented on company’s revised guidance, "Weaker second
quarter bookings will not support our previously guided second half revenue targets. As a result, we are lowering our second
half numbers, but remain optimistic about potential fourth quarter business. With a healthy number of contract renewals in
the fourth quarter, we expect a rebound that should produce good earnings and allow us to grow our backlog."
AUGUST 5th, 2005
Cadence Reports 12 Percent Revenue Gain over Last Year
Cadence Design Systems, Inc. (NYSE:CDN)(NASDAQ:CDN), one of the largest components of the electronic
design automation market, reported revenue of $321 million for its latest quarter, its second quarter, ended July 2, 2005.
This represented an increase of 12 percent over the $287 million in revenue the company recorded for its second quarter of
2004.
Mike Fister, president and CEO of Cadence Design Systems, Inc. commented
on the results from a geographic and global account perspective, "We saw good growth in both our global accounts and geographic
regions during the second quarter, confirming for us that both our technologies and our strategies are well positioned to
help all types of customers meet their market demands," "We are looking forward to CDNLive!, our new expanded user group meeting
in September, where we will share more about our new technology and products with our customers."
Bill Porter, senior vice president and chief financial officer commented
on product performance, "Once again in the second quarter, we saw good results across our product portfolio with particular
strength in custom IC as well as digital and verification. Our diversified portfolio is a significant driver of our consistent
results."
As far as product segment revenue went, Cadence reported that that
their customs design tool revenue was 31 percent of total sales for its second quarter of 2005, compared to 24 percent of
total sales in its first quarter of 2005. For the second quarter of 2004, custom design tools stood at 27 percent of total
revenues. Cadence’s custom design tools address the analog and mixed signal integrated circuit development and the custom digital integrated circuit design markets.
Cadence other product segment revenue were either slightly down
or flat in terms of a percentage of total revenues from the first quarter to the second quarter of this year Cadence’s
major product segments include Functional Verification, Digital IC Design, Custom IC Design, Design for Manufacturing, System
Interconnect, Services and Other. The product segment revenue includes software maintenance revenue.
For the third quarter of 2005, Cadence has projected total revenue
somewhere between $320 million to $330 million. For its 2005 year, the company foresees revenue between $1.275 billion and
$1.215 billion.
August 4th, 2005
IntelliSense Introduces Complete Top-Down Design
Tool – Ties System Architectural Level to MEMS
and Nanotechnology Levels - Includes Features for Package, Process and Test Engineers
IntelliSense has made available IntelliSuite v8, a tool it calls
a bottom-up process-driven design and top down synthesis tool. The tool has been designed to meet the needs of a wide variety
of engineers across a technology organization. Program managers, system architects, electronic designer, package designers,
device level designers, process engineers, test engineers and manufacturing engineers can all access the Living Design Environment
of the tool to determine how their design contributions will affect the final viability of the design.
The IntelliSuite also includes a simulator, called SYNPLE, that
has been designed for the implementation of micromachine and nanotechnology oriented structures into digital and mixed signal
integrated circuits. The simulator ships with element libraries that range from standard analog and digital electric circuit
design blocks, to mechanical inertia devices needed for MEMs design to biological modules used for the implementation of microfluidic
based microsystems. The tool also includes the MEMS-SoC Constructor Kit -- System-on-a-Chip design kit, which includes a library
of Verilog-A models that is used to create mixed signal integrated chips complete with on-chip MEMs devices.
There are many other features of the new design tool. For the process
engineer, there is the RIE/ICP and Bosch process etch simulator. For the layout engineer, there is IntelliMask Pro, a MEMS
layout tool, which combines IC and MEMS layout together.
For those concerned with cost and manufacturing economics, the tool
also includes a Cost Model tool, which permits managers and engineers to determine the best manufacturing process development
and production strategy to maximize yield and minimize production costs.
IntelliSense, besides its integrated MEMS / IC design software also
offers design, IP licensing and consulting services.
JULY 26th, 2005
In what has been a mundane year for EDA companies, Synplicity, Inc.
(NASDAQ:SYNP), has broken away from the crowd with an “EDA significant” rise in revenue. The company reported
that for both the quarter ended and the six months ended June 30, 2005, the company’s revenue rose 7 percent year-over-year.
For the quarter ended June 30, 2005, the company noted a 4 percent sequential gain over the last quarter. Revenues for the
second quarter ended June 30, 2005 was $15.2 million. For the six months ended June 30, 2005, revenue was $29.7 million.
Gary Meyers, President and CEO specifically pointed out the triple
digit booking gains for the company’s structured ASIC design tools, "In the second quarter, we continued to grow revenues
and profits. In the FPGA line of business we had strong sequential and year over year bookings growth of the Synplify Pro
and Identify product lines. We also had more than 100 percent year over year bookings growth for the structured ASIC product
line and sold a record number of structured ASIC licenses. As we look to the remainder of 2005, we are focused on continuing
to drive growth and profitability."
Looking forward, Synplicity projects that revenue for the third
quarter would rise again to somewhere around $15.8 million. For the year, total revenues are estimated at between $62 million
and $63 million – higher than previous guidance.
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